riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-09-14	target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'	Peter Maydell	2	-2/+2
2022-09-14	target/arm: Support 64-bit event counters for FEAT_PMUv3p5	Peter Maydell	3	-9/+57
2022-09-14	target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits	Peter Maydell	2	-4/+37
2022-09-14	target/arm: Rename pmu_8_n feature test functions	Peter Maydell	2	-17/+17
2022-09-14	target/arm: Detect overflow when calculating next PMU interrupt	Peter Maydell	1	-8/+14
2022-09-14	target/arm: Honour MDCR_EL2.HPMD in Secure EL2	Peter Maydell	1	-10/+7
2022-09-14	target/arm: Ignore PMCR.D when PMCR.LC is set	Peter Maydell	1	-4/+13
2022-09-14	target/arm: Don't mishandle count when enabling or disabling PMU counters	Peter Maydell	1	-0/+45
2022-09-14	target/arm: Correct value returned by pmu_counter_mask()	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Add missing space in comment	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Advertise FEAT_ETS for '-cpu max'	Peter Maydell	2	-0/+5
2022-09-14	target/arm: Implement ID_DFR1	Peter Maydell	3	-2/+5
2022-09-14	target/arm: Implement ID_MMFR5	Peter Maydell	3	-2/+5
2022-09-14	target/arm: Sort KVM reads of AArch32 ID registers into encoding order	Peter Maydell	1	-2/+2
2022-09-14	target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8	Peter Maydell	1	-5/+60
2022-09-14	target/arm: Add cortex-a35	Hao Wu	1	-0/+80
2022-09-07	target/riscv: Update the privilege field for sscofpmf CSRs	Atish Patra	1	-30/+60
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra	2	-0/+58
2022-09-07	target/riscv: Add few cache related PMU events	Atish Patra	1	-0/+25
2022-09-07	target/riscv: Simplify counter predicate function	Atish Patra	1	-101/+9
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra	7	-11/+623
2022-09-07	target/riscv: Add vstimecmp support	Atish Patra	6	-6/+118
2022-09-07	target/riscv: Add stimecmp support	Atish Patra	8	-1/+235
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra	2	-5/+2
2022-09-07	target/riscv: Use official extension names for AIA CSRs	Anup Patel	4	-14/+26
2022-09-07	target/riscv: Add xicondops in ISA entry	Rahul Pathak	1	-0/+1
2022-09-07	target/riscv: Remove additional priv version check for mcountinhibit	Atish Patra	1	-8/+0
2022-09-07	target/riscv: Fix priority of csr related check in riscv_csrrw_check	Weiwei Li	1	-19/+25
2022-09-07	target/riscv: Add Zihintpause support	Dao Lu	4	-1/+25
2022-09-07	target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...	eopXD	1	-0/+1
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen	2	-2/+25
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen	2	-0/+14
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen	2	-0/+38
2022-09-07	target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...	Yueh-Ting (eop) Chen	1	-10/+16
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen	2	-0/+11
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen	2	-0/+8
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen	2	-0/+5
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen	2	-11/+29
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen	6	-2/+20
2022-09-07	target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V	Alexey Baturo	1	-1/+1
2022-09-07	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...	Weiwei Li	1	-13/+5
2022-09-07	target/riscv: Fix checks in hmode/hmode32	Weiwei Li	2	-7/+7
2022-09-07	target/riscv: Add check for csrs existed with U extension	Weiwei Li	1	-3/+21
2022-09-07	target/riscv: Fix checkpatch warning may triggered in csr_ops table	Weiwei Li	1	-207/+234
2022-09-07	target/riscv: H extension depends on I extension	Weiwei Li	1	-0/+6
2022-09-07	target/riscv: Add check for supported privilege mode combinations	Weiwei Li	1	-0/+6
2022-09-07	target/riscv: move zmmul out of the experimental properties	Weiwei Li	1	-1/+2
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot	2	-5/+22
2022-09-07	target/riscv: Force disable extensions if priv spec version does not match	Anup Patel	1	-56/+94