riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-10-27	linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI	Richard Henderson	2	-2/+7
2020-10-27	target/rx: Fix Lesser GPL version number	Chetan Pant	1	-1/+1
2020-10-27	target/rx: Fix some comment spelling errors	Lichang Zhao	2	-2/+2
2020-10-27	target/sh4: fix some comment spelling errors	Lichang Zhao	3	-3/+3
2020-10-27	target/sh4: Update coding style to make checkpatch.pl happy	Philippe Mathieu-Daudé	2	-6/+10
2020-10-26	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20201026' into staging	Peter Maydell	4	-2/+14
2020-10-26	target/xtensa: enable all coprocessors for linux-user	Max Filippov	1	-0/+1
2020-10-22	target/riscv: raise exception to HS-mode at get_physical_address	Yifei Jiang	2	-12/+34
2020-10-22	target/riscv: Fix implementation of HLVX.WU instruction	Georg Kotheimer	1	-3/+3
2020-10-22	target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt	Georg Kotheimer	1	-1/+3
2020-10-22	target/riscv: Fix update of hstatus.SPVP	Georg Kotheimer	1	-1/+1
2020-10-22	riscv: Convert interrupt logs to use qemu_log_mask()	Alistair Francis	2	-2/+7
2020-10-22	s390x: pv: Fix diag318 PV fencing	Janosch Frank	4	-2/+14
2020-10-20	target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension	Peter Maydell	3	-0/+16
2020-10-20	target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16	Peter Maydell	1	-19/+28
2020-10-20	target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile	Peter Maydell	1	-12/+19
2020-10-20	target/arm: Implement v8.1M low-overhead-loop instructions	Peter Maydell	2	-2/+99
2020-10-20	target/arm: Implement v8.1M branch-future insns (as NOPs)	Peter Maydell	3	-1/+38
2020-10-20	target/arm: Don't allow BLX imm for M-profile	Peter Maydell	1	-0/+8
2020-10-20	target/arm: Make the t32 insn[25:23]=111 group non-overlapping	Peter Maydell	1	-13/+11
2020-10-20	target/arm: Implement v8.1M conditional-select insns	Peter Maydell	2	-0/+63
2020-10-20	target/arm: Implement v8.1M NOCP handling	Peter Maydell	3	-6/+22
2020-10-20	target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11	Richard Henderson	2	-8/+10
2020-10-20	target/arm: Fix reported EL for mte_check_fail	Richard Henderson	1	-7/+3
2020-10-20	target/arm: Remove redundant mmu_idx lookup	Richard Henderson	1	-2/+1
2020-10-20	target/arm: Use tlb_flush_page_bits_by_mmuidx*	Richard Henderson	1	-7/+39
2020-10-20	target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest	Peter Maydell	3	-13/+47
2020-10-20	target/arm: Fix SMLAD incorrect setting of Q bit	Peter Maydell	1	-11/+49
2020-10-19	Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' ...	Peter Maydell	9	-109/+756
2020-10-17	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	1	-0/+1
2020-10-17	hax: unbreak accelerator cpu code after cpus.c split	Claudio Fontana	1	-0/+1
2020-10-17	target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)	Philippe Mathieu-Daudé	1	-1/+1
2020-10-17	target/mips/cpu: Display warning when CPU is used without input clock	Philippe Mathieu-Daudé	1	-0/+10
2020-10-17	target/mips/cpu: Introduce mips_cpu_create_with_clock() helper	Philippe Mathieu-Daudé	2	-0/+24
2020-10-17	target/mips/cpu: Allow the CPU to use dynamic frequencies	Philippe Mathieu-Daudé	2	-2/+13
2020-10-17	target/mips/cpu: Make cp0_count_rate a property	Philippe Mathieu-Daudé	2	-8/+20
2020-10-17	target/mips/cpu: Calculate the CP0 timer period using the CPU frequency	Philippe Mathieu-Daudé	1	-2/+2
2020-10-17	target/mips: Move cp0_count_ns to CPUMIPSState	Philippe Mathieu-Daudé	3	-17/+28
2020-10-17	target/mips/cp0_timer: Document TIMER_PERIOD origin	Philippe Mathieu-Daudé	1	-1/+11
2020-10-17	target/mips/cp0_timer: Explicit unit in variable name	Philippe Mathieu-Daudé	1	-9/+10
2020-10-17	target/mips: Move cpu_mips_get_random() with CP0 helpers	Philippe Mathieu-Daudé	3	-26/+26
2020-10-17	target/mips/op_helper: Log unimplemented cache opcode	Philippe Mathieu-Daudé	1	-0/+9
2020-10-17	target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op	Philippe Mathieu-Daudé	1	-0/+5
2020-10-17	target/mips/op_helper: Convert multiple if() to switch case	Philippe Mathieu-Daudé	1	-4/+9
2020-10-17	target/mips: Add loongson-ext lsdc2 group of instructions	Jiaxun Yang	1	-0/+179
2020-10-17	target/mips: Add loongson-ext lswc2 group of instructions (Part 2)	Jiaxun Yang	1	-2/+180
2020-10-17	target/mips: Add loongson-ext lswc2 group of instructions (Part 1)	Jiaxun Yang	1	-0/+86
2020-10-17	target/mips: Demacro helpers for <MAX\|MAXA\|MIN\|MINA>.<D\|S>	Aleksandar Markovic	1	-23/+81
2020-10-17	target/mips: Demacro helpers for M<ADD\|SUB>F.<D\|S>	Aleksandar Markovic	1	-17/+46
2020-10-17	target/mips: Demacro helpers for <ABS\|CHS>.<D\|S\|PS>	Aleksandar Markovic	1	-21/+40