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2021-06-21target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstubRichard Henderson1-13/+2
2021-06-21target/s390x: Improve s390_cpu_dump_state vs cc_opRichard Henderson1-5/+7
2021-06-21target/s390x: Do not modify cpu state in s390_cpu_get_psw_maskRichard Henderson1-4/+4
2021-06-21target/s390x: Expose load_psw and get_psw_mask to cpu.hRichard Henderson6-61/+69
2021-06-21s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2David Hildenbrand2-8/+11
2021-06-21s390x/tcg: We support Vector enhancements facilityDavid Hildenbrand1-0/+1
2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand5-0/+391
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand4-2/+49
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand3-8/+87
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand3-2/+70
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand1-33/+73
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand3-1/+30
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand3-3/+30
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand3-9/+77
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand3-12/+121
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand3-15/+109
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand3-14/+153
2021-06-21s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand2-0/+52
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand4-0/+33
2021-06-21s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand1-11/+12
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand3-25/+8
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand3-22/+6
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand3-32/+20
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand3-24/+13
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand3-107/+38
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand3-156/+58
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand3-79/+30
2021-06-21s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand1-2/+2
2021-06-21s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand2-6/+43
2021-06-21s390x/kvm: remove unused gs handlingCornelia Huck3-15/+1
2021-06-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell4-50/+94
2021-06-16bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell1-20/+0
2021-06-16target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell3-99/+109
2021-06-16target/arm: Add framework for MVE decodePeter Maydell5-0/+53
2021-06-16target/arm: Implement MVE LETP insnPeter Maydell2-9/+97
2021-06-16target/arm: Implement MVE DLSTPPeter Maydell2-5/+27
2021-06-16target/arm: Implement MVE WLSTP insnPeter Maydell2-3/+42
2021-06-16target/arm: Implement MVE LCTPPeter Maydell2-0/+26
2021-06-16target/arm: Let vfp_access_check() handle late NOCP checksPeter Maydell1-5/+15
2021-06-16target/arm: Add handling for PSR.ECI/ICIPeter Maydell5-5/+133
2021-06-16target/arm: Handle VPR semantics in existing codePeter Maydell3-11/+57
2021-06-16target/arm: Enable FPSCR.QC bit for MVEPeter Maydell2-10/+23
2021-06-16target/arm: Provide and use H8 and H1_8 macrosPeter Maydell3-137/+143
2021-06-16target/arm: Fix mte page crossing testRichard Henderson1-1/+1
2021-06-16target/i386: Added Intercept CR0 writes checkLara Lazier1-0/+9
2021-06-16target/i386: Added consistency checks for CR0Lara Lazier3-3/+13
2021-06-16target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier1-0/+10
2021-06-16target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier2-47/+62
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson1-30/+48
2021-06-15target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson1-1/+0
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