riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-03-15	target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXIT	Richard Henderson	1	-14/+28
2019-03-15	target/arm: Check access permission to ADDVL/ADDPL/RDVL	Amir Charif	1	-8/+14
2019-03-15	target/arm: change arch timer registers access permission	Dongjiu Geng	1	-15/+15
2019-03-13	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...	Peter Maydell	12	-1589/+2891
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann	1	-20/+1
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann	1	-34/+0
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann	3	-18/+18
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann	2	-211/+164
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann	2	-71/+81
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann	3	-30/+34
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann	3	-100/+108
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann	2	-11/+24
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann	2	-16/+25
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann	2	-60/+33
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann	2	-39/+27
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann	3	-81/+134
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann	3	-117/+195
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann	4	-38/+154
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann	3	-56/+126
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann	3	-600/+91
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann	3	-0/+389
2019-03-13	target/riscv: Convert RV64F insns to decodetree	Bastian Koppelmann	2	-0/+66
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann	3	-0/+415
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann	3	-144/+71
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann	3	-0/+178
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann	4	-9/+137
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann	3	-42/+88
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann	3	-12/+21
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann	4	-9/+206
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann	4	-10/+50
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann	2	-0/+58
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann	3	-11/+69
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann	4	-14/+92
2019-03-12	target/hppa: exit TB if either Data or Instruction TLB changes	Sven Schnelle	1	-4/+3
2019-03-12	target/hppa: add TLB protection id check	Sven Schnelle	6	-9/+70
2019-03-12	target/hppa: allow multiple itlbp without itlba	Sven Schnelle	1	-1/+1
2019-03-12	target/hppa: fix b,gate instruction	Sven Schnelle	1	-1/+12
2019-03-12	target/hppa: ignore DIAG opcode	Sven Schnelle	2	-0/+10
2019-03-12	target/hppa: remove PSW I/R/Q bit check	Sven Schnelle	1	-5/+0
2019-03-12	target/hppa: add TLB trace events	Sven Schnelle	3	-2/+39
2019-03-12	target/hppa: report ITLB_EXCP_MISS for ITLB misses	Sven Schnelle	1	-3/+1
2019-03-12	target/hppa: fix TLB handling for page 0	Sven Schnelle	1	-5/+7
2019-03-12	target/hppa: fix overwriting source reg in addb	Sven Schnelle	1	-1/+3
2019-03-12	target/hppa: Check for page crossings in use_goto_tb	Richard Henderson	1	-6/+4
2019-03-12	spapr: Use CamelCase properly	David Gibson	1	-2/+2
2019-03-12	target/ppc: Optimize x[sv]xsigdp using deposit_i64()	Philippe Mathieu-Daudé	1	-8/+4
2019-03-12	target/ppc: Optimize xviexpdp() using deposit_i64()	Philippe Mathieu-Daudé	1	-11/+3
2019-03-12	target/ppc: add HV support for POWER9	Cédric Le Goater	1	-1/+2
2019-03-12	target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_c...	Mark Cave-Ayland	2	-40/+14
2019-03-12	target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian...	Mark Cave-Ayland	3	-10/+10