riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-02	target/mips: Restrict mmu_init() to TCG	Philippe Mathieu-Daudé	3	-4/+3
2021-05-02	target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder	Philippe Mathieu-Daudé	7	-167/+179
2021-05-02	target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG	Philippe Mathieu-Daudé	2	-4/+9
2021-05-02	target/mips: Move physical addressing code to sysemu/physaddr.c	Philippe Mathieu-Daudé	4	-255/+282
2021-05-02	target/mips: Move sysemu specific files under sysemu/ subfolder	Philippe Mathieu-Daudé	5	-6/+11
2021-05-02	target/mips: Move cpu_signal_handler definition around	Philippe Mathieu-Daudé	1	-5/+4
2021-05-02	target/mips: Add simple user-mode mips_cpu_tlb_fill()	Philippe Mathieu-Daudé	2	-10/+36
2021-05-02	target/mips: Add simple user-mode mips_cpu_do_interrupt()	Philippe Mathieu-Daudé	5	-5/+39
2021-05-02	target/mips: Introduce tcg-internal.h for TCG specific declarations	Philippe Mathieu-Daudé	2	-4/+23
2021-05-02	target/mips: Extract load/store helpers to ldst_helper.c	Philippe Mathieu-Daudé	3	-259/+289
2021-05-02	target/mips: Merge do_translate_address into cpu_mips_translate_address	Philippe Mathieu-Daudé	3	-24/+9
2021-05-02	target/mips: Declare mips_env_set_pc() inlined in "internal.h"	Philippe Mathieu-Daudé	3	-20/+14
2021-05-02	target/mips: Turn printfpr() macro into a proper function	Philippe Mathieu-Daudé	1	-27/+23
2021-05-02	target/mips: Restrict mips_cpu_dump_state() to cpu.c	Philippe Mathieu-Daudé	3	-78/+77
2021-05-02	target/mips: Optimize CPU/FPU regnames[] arrays	Philippe Mathieu-Daudé	3	-4/+4
2021-05-02	target/mips: Make CPU/FPU regnames[] arrays global	Philippe Mathieu-Daudé	4	-14/+17
2021-05-02	target/mips: Move msa_reset() to new source file	Philippe Mathieu-Daudé	3	-36/+61
2021-05-02	target/mips: Move IEEE rounding mode array to new source file	Philippe Mathieu-Daudé	3	-8/+19
2021-05-02	target/mips: Simplify meson TCG rules	Philippe Mathieu-Daudé	1	-3/+2
2021-05-02	target/mips: Make check_cp0_enabled() return a boolean	Philippe Mathieu-Daudé	2	-2/+9
2021-05-02	target/mips: Migrate missing CPU fields	Philippe Mathieu-Daudé	1	-6/+15
2021-05-02	target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode	Philippe Mathieu-Daudé	1	-0/+1
2021-05-02	target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes	Philippe Mathieu-Daudé	1	-0/+2
2021-05-02	target/mips: Fix CACHEE opcode (CACHE using EVA addressing)	Philippe Mathieu-Daudé	1	-1/+3
2021-04-30	target/arm: Enforce alignment for sve LD1R	Richard Henderson	1	-1/+1
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (single)	Richard Henderson	1	-4/+5
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)	Richard Henderson	1	-4/+11
2021-04-30	target/arm: Use MemOp for size + endian in aa64 vector ld/st	Richard Henderson	1	-10/+10
2021-04-30	target/arm: Enforce alignment for aa64 load-acq/store-rel	Richard Henderson	1	-9/+14
2021-04-30	target/arm: Use finalize_memop for aa64 fpr load/store	Richard Henderson	1	-16/+26
2021-04-30	target/arm: Use finalize_memop for aa64 gpr load/store	Richard Henderson	1	-45/+33
2021-04-30	target/arm: Enforce alignment for VLDn/VSTn (single)	Richard Henderson	1	-6/+42
2021-04-30	target/arm: Enforce alignment for VLDn/VSTn (multiple)	Richard Henderson	1	-5/+22
2021-04-30	target/arm: Enforce alignment for VLDn (all lanes)	Richard Henderson	3	-9/+44
2021-04-30	target/arm: Enforce alignment for VLDR/VSTR	Richard Henderson	1	-6/+6
2021-04-30	target/arm: Enforce alignment for VLDM/VSTM	Richard Henderson	1	-4/+4
2021-04-30	target/arm: Enforce alignment for SRS	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for RFE	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for LDM/STM	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce alignment for LDA/LDAH/STL/STLH	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Enforce word alignment for LDRD/STRD	Richard Henderson	1	-8/+8
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness	Richard Henderson	2	-35/+49
2021-04-30	target/arm: Fix SCTLR_B test for TCGv_i64 load/store	Richard Henderson	1	-2/+2
2021-04-30	target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64	Richard Henderson	1	-20/+15
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness	Richard Henderson	3	-52/+77
2021-04-30	target/arm: Add ALIGN_MEM to TBFLAG_ANY	Richard Henderson	5	-6/+25
2021-04-30	target/arm: Move TBFLAG_ANY bits to the bottom	Richard Henderson	1	-7/+7
2021-04-30	target/arm: Move TBFLAG_AM32 bits to the top	Richard Henderson	1	-21/+21
2021-04-30	target/arm: Move mode specific TB flags to tb->cs_base	Richard Henderson	3	-26/+35
2021-04-30	target/arm: Introduce CPUARMTBFlags	Richard Henderson	5	-37/+57