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AgeCommit message (Expand)AuthorFilesLines
2020-02-28target/arm: Implement ARMv8.3-CCIDXPeter Maydell2-1/+35
2020-02-28target/arm: Implement v8.4-RCPCPeter Maydell3-1/+96
2020-02-28target/arm: Implement v8.3-RCPCPeter Maydell3-0/+30
2020-02-28target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0Peter Maydell1-2/+2
2020-02-28target/arm: Split VMINMAXNM decodeRichard Henderson2-77/+44
2020-02-28target/arm: Split VFM decodeRichard Henderson2-14/+55
2020-02-28target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson1-90/+60
2020-02-28target/arm: Remove ARM_FEATURE_VFP*Richard Henderson5-37/+0
2020-02-28target/arm: Move the vfp decodetree calls next to the base isaRichard Henderson1-54/+29
2020-02-28target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson3-44/+50
2020-02-28target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insnRichard Henderson1-4/+0
2020-02-28target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson4-6/+36
2020-02-28target/arm: Add missing checks for fpsp_v2Richard Henderson1-9/+69
2020-02-28target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson1-16/+8
2020-02-28target/arm: Perform fpdp_v2 check firstRichard Henderson1-69/+71
2020-02-28target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson3-5/+20
2020-02-28target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}Richard Henderson1-0/+18
2020-02-28target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson2-22/+22
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson5-14/+25
2020-02-28target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfnRichard Henderson1-0/+1
2020-02-27Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200227' into stagingPeter Maydell7-17/+64
2020-02-27s390x: Rename and use constants for short PSW address and maskJanosch Frank2-3/+4
2020-02-26s390/sclp: improve special wait psw logicChristian Borntraeger1-1/+1
2020-02-26s390x: Add missing vcpu reset functionsJanosch Frank4-12/+58
2020-02-26target/s390x/translate: Fix RNSBG instructionThomas Huth1-1/+1
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée2-23/+25
2020-02-25Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEADPaolo Bonzini7-19/+18
2020-02-25target/i386: check for empty register in FXAMPaolo Bonzini1-1/+5
2020-02-21target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson1-4/+6
2020-02-21target/arm: Use isar_feature_aa32_simd_r32 more placesRichard Henderson3-13/+11
2020-02-21target/arm: Rename isar_feature_aa32_simd_r32Richard Henderson2-27/+28
2020-02-21target/arm: Convert PMULL.8 to gvecRichard Henderson6-55/+95
2020-02-21target/arm: Convert PMULL.64 to gvecRichard Henderson5-72/+39
2020-02-21target/arm: Convert PMUL.8 to gvecRichard Henderson5-37/+39
2020-02-21target/arm: Vectorize USHL and SSHLRichard Henderson6-66/+389
2020-02-21target/arm: Correctly implement ACTLR2, HACTLR2Peter Maydell4-9/+33
2020-02-21target/arm: Use FIELD_EX32 for testing 32-bit fieldsPeter Maydell1-9/+9
2020-02-21target/arm: Use isar_feature function for testing AA32HPD featurePeter Maydell2-2/+7
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell6-79/+106
2020-02-21target/arm: Correct handling of PMCR_EL0.LC bitPeter Maydell1-4/+9
2020-02-21target/arm: Correct definition of PMCRDPPeter Maydell1-1/+2
2020-02-21target/arm: Provide ARMv8.4-PMU in '-cpu max'Peter Maydell1-0/+8
2020-02-21target/arm: Implement ARMv8.4-PMU extensionPeter Maydell2-1/+39
2020-02-21target/arm: Implement ARMv8.1-PMU extensionPeter Maydell1-2/+30
2020-02-21target/arm: Read debug-related ID registers from KVMPeter Maydell3-0/+49
2020-02-21target/arm: Move DBGDIDR into ARMISARegistersPeter Maydell5-12/+12
2020-02-21target/arm: Stop assuming DBGDIDR always existsPeter Maydell4-19/+57
2020-02-21target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checksPeter Maydell4-11/+25
2020-02-21target/arm: Define an aa32_pmu_8_1 isar feature test functionPeter Maydell4-21/+27
2020-02-21target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON fieldPeter Maydell1-1/+1