riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-09-23	target/s390x: support SHA-512 extensions	Jason A. Donenfeld	2	-1/+237
2022-09-23	s390x/tcg: Fix opcode for lzrf	Christian Borntraeger	1	-1/+1
2022-09-22	Merge tag 'pull-hex-20220919' of https://github.com/quic/qemu into staging	Stefan Hajnoczi	1	-23/+0
2022-09-21	Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ...	Stefan Hajnoczi	5	-89/+118
2022-09-21	Merge tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu into staging	Stefan Hajnoczi	12	-81/+272
2022-09-21	target/m68k: always call gen_exit_tb() after writes to SR	Mark Cave-Ayland	1	-0/+4
2022-09-21	target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K	Mark Cave-Ayland	5	-74/+75
2022-09-21	target/m68k: Perform writback before modifying SR	Richard Henderson	1	-3/+5
2022-09-21	target/m68k: Fix MACSR to CCR	Richard Henderson	1	-2/+4
2022-09-21	target/m68k: Implement atomic test-and-set	Richard Henderson	1	-10/+30
2022-09-20	target/ppc: Clear fpstatus flags on helpers missing it	Víctor Colombo	1	-11/+26
2022-09-20	target/ppc: Zero second doubleword of VSR registers for FPR insns	Víctor Colombo	1	-0/+8
2022-09-20	target/ppc: Set OV32 when OV is set	Víctor Colombo	1	-2/+2
2022-09-20	target/ppc: Zero second doubleword for VSX madd instructions	Víctor Colombo	1	-1/+1
2022-09-20	target/ppc: Set result to QNaN for DENBCD when VXCVI occurs	Víctor Colombo	1	-2/+24
2022-09-20	target/ppc: Zero second doubleword in DFP instructions	Víctor Colombo	1	-1/+4
2022-09-20	target/ppc: Remove unused xer_* macros	Víctor Colombo	1	-4/+0
2022-09-20	target/ppc: Remove extra space from s128 field in ppc_vsr_t	Víctor Colombo	1	-1/+1
2022-09-20	target/ppc: Merge fsqrt and fsqrts helpers	Víctor Colombo	3	-26/+17
2022-09-20	target/ppc: Move fsqrts to decodetree	Víctor Colombo	3	-23/+2
2022-09-20	target/ppc: Move fsqrt to decodetree	Víctor Colombo	3	-13/+24
2022-09-20	target/ppc: Implement hashstp and hashchkp	Víctor Colombo	4	-0/+8
2022-09-20	target/ppc: Implement hashst and hashchk	Víctor Colombo	5	-0/+128
2022-09-20	target/ppc: Add HASHKEYR and HASHPKEYR SPRs	Víctor Colombo	2	-0/+30
2022-09-19	Hexagon (target/hexagon) remove unused encodings	Taylor Simpson	1	-23/+0
2022-09-19	target/i386: introduce insn_get_addr	Paolo Bonzini	1	-10/+26
2022-09-19	target/i386: REPZ and REPNZ are mutually exclusive	Paolo Bonzini	1	-0/+2
2022-09-19	target/i386: fix INSERTQ implementation	Paolo Bonzini	3	-8/+18
2022-09-19	target/i386: correctly mask SSE4a bit indices in register operands	Paolo Bonzini	1	-2/+2
2022-09-18	target/i386: Raise #GP on unaligned m128 accesses when required.	Paolo Bonzini	6	-29/+72
2022-09-17	Merge tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	14	-520/+182
2022-09-14	target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'	Peter Maydell	2	-2/+2
2022-09-14	target/arm: Support 64-bit event counters for FEAT_PMUv3p5	Peter Maydell	3	-9/+57
2022-09-14	target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits	Peter Maydell	2	-4/+37
2022-09-14	target/arm: Rename pmu_8_n feature test functions	Peter Maydell	2	-17/+17
2022-09-14	target/arm: Detect overflow when calculating next PMU interrupt	Peter Maydell	1	-8/+14
2022-09-14	target/arm: Honour MDCR_EL2.HPMD in Secure EL2	Peter Maydell	1	-10/+7
2022-09-14	target/arm: Ignore PMCR.D when PMCR.LC is set	Peter Maydell	1	-4/+13
2022-09-14	target/arm: Don't mishandle count when enabling or disabling PMU counters	Peter Maydell	1	-0/+45
2022-09-14	target/arm: Correct value returned by pmu_counter_mask()	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Add missing space in comment	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Advertise FEAT_ETS for '-cpu max'	Peter Maydell	2	-0/+5
2022-09-14	target/arm: Implement ID_DFR1	Peter Maydell	3	-2/+5
2022-09-14	target/arm: Implement ID_MMFR5	Peter Maydell	3	-2/+5
2022-09-14	target/arm: Sort KVM reads of AArch32 ID registers into encoding order	Peter Maydell	1	-2/+2
2022-09-14	target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8	Peter Maydell	1	-5/+60
2022-09-14	target/arm: Add cortex-a35	Hao Wu	1	-0/+80
2022-09-13	target/riscv: Honour -semihosting-config userspace=on and enable=on	Peter Maydell	3	-7/+6
2022-09-13	target/xtensa: Honour -semihosting-config userspace=on	Peter Maydell	1	-3/+4