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2020-06-26target/arm: Move regime_el to internals.hRichard Henderson2-36/+36
2020-06-26target/arm: Implement the access tag cache flushesRichard Henderson1-0/+65
2020-06-26target/arm: Implement the LDGM, STGM, STZGM instructionsRichard Henderson4-8/+153
2020-06-26target/arm: Simplify DC_ZVARichard Henderson1-70/+26
2020-06-26target/arm: Restrict the values of DCZID.BS under TCGRichard Henderson1-0/+24
2020-06-26target/arm: Implement the STGP instructionRichard Henderson1-3/+26
2020-06-26target/arm: Implement LDG, STG, ST2G instructionsRichard Henderson5-5/+386
2020-06-26target/arm: Define arm_cpu_do_unaligned_access for user-onlyRichard Henderson2-3/+3
2020-06-26target/arm: Implement the SUBP instructionRichard Henderson1-2/+22
2020-06-26target/arm: Implement the GMI instructionRichard Henderson1-0/+15
2020-06-26target/arm: Implement the ADDG, SUBG instructionsRichard Henderson4-0/+71
2020-06-26target/arm: Revise decoding for disas_add_sub_immRichard Henderson1-15/+8
2020-06-26target/arm: Implement the IRG instructionRichard Henderson5-0/+98
2020-06-26target/arm: Add MTE bits to tb_flagsRichard Henderson5-4/+75
2020-06-26target/arm: Add MTE system registersRichard Henderson4-0/+128
2020-06-26target/arm: Add DISAS_UPDATE_NOCHAINRichard Henderson3-0/+9
2020-06-26target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXITRichard Henderson4-18/+20
2020-06-26target/arm: Add support for MTE to HCR_EL2 and SCR_EL3Richard Henderson1-3/+11
2020-06-26target/arm: Add support for MTE to SCTLR_ELxRichard Henderson1-6/+17
2020-06-26target/arm: Improve masking of SCR RES0 bitsRichard Henderson1-7/+8
2020-06-26target/arm: Add isar tests for mteRichard Henderson1-0/+10
2020-06-26Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200626' into...Peter Maydell1-5/+0
2020-06-26target/ppc: Remove TIDR from POWER10 processorCédric Le Goater1-5/+0
2020-06-25Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into stagingPeter Maydell3-23/+46
2020-06-23target/arm: Check supported KVM features globally (not per vCPU)Philippe Mathieu-Daudé5-29/+22
2020-06-23target/arm: Remove dead code relating to SABA and UABAPeter Maydell1-12/+0
2020-06-23target/arm: Remove unnecessary gen_io_end() callsPeter Maydell3-8/+4
2020-06-23target/arm: Move some functions used only in translate-neon.inc.c to that filePeter Maydell2-101/+101
2020-06-23target/arm: Convert Neon VTRN to decodetreePeter Maydell3-362/+93
2020-06-23target/arm: Convert Neon VSWP to decodetreePeter Maydell3-4/+44
2020-06-23target/arm: Convert Neon 2-reg-misc VCVT insns to decodetreePeter Maydell3-62/+87
2020-06-23target/arm: Convert Neon 2-reg-misc VRINT insns to decodetreePeter Maydell3-26/+74
2020-06-23target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetreePeter Maydell3-45/+39
2020-06-23target/arm: Convert simple fp Neon 2-reg-misc insnsPeter Maydell4-49/+78
2020-06-23target/arm: Convert Neon VQABS, VQNEG to decodetreePeter Maydell3-28/+40
2020-06-23target/arm: Convert remaining simple 2-reg-misc Neon opsPeter Maydell3-31/+86
2020-06-23target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetreePeter Maydell4-10/+60
2020-06-23target/arm: Make gen_swap_half() take separate src and destPeter Maydell2-6/+6
2020-06-23target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefsPeter Maydell3-5/+5
2020-06-23target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFnPeter Maydell2-3/+3
2020-06-23target/arm: Convert Neon 2-reg-misc crypto operations to decodetreePeter Maydell3-48/+58
2020-06-23target/arm: Convert vectorised 2-reg-misc Neon ops to decodetreePeter Maydell3-27/+74
2020-06-23target/arm: Convert Neon VCVT f16/f32 insns to decodetreePeter Maydell3-62/+102
2020-06-23target/arm: Convert Neon 2-reg-misc VSHLL to decodetreePeter Maydell3-34/+55
2020-06-23target/arm: Convert Neon narrowing moves to decodetreePeter Maydell3-79/+70
2020-06-23target/arm: Convert VZIP, VUZP to decodetreePeter Maydell3-90/+79
2020-06-23target/arm: Convert Neon 2-reg-misc pairwise ops to decodetreePeter Maydell3-33/+157
2020-06-23target/arm: Convert Neon 2-reg-misc VREV64 to decodetreePeter Maydell3-22/+64
2020-06-22target/xtensa: drop gen_io_end callMax Filippov1-3/+0
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-8/+8