index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2020-02-27
target/riscv: Mark both sstatus and msstatus_hs as dirty
Alistair Francis
1
-0
/
+13
2020-02-27
target/riscv: Disable guest FP support based on virtual status
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Only set TB flags with FP status if enabled
Alistair Francis
1
-1
/
+4
2020-02-27
target/riscv: Remove the hret instruction
Alistair Francis
2
-6
/
+0
2020-02-27
target/riscv: Add hfence instructions
Alistair Francis
2
-9
/
+54
2020-02-27
target/riscv: Add Hypervisor trap return support
Alistair Francis
1
-10
/
+52
2020-02-27
target/riscv: Add hypvervisor trap support
Alistair Francis
1
-10
/
+59
2020-02-27
target/riscv: Generate illegal instruction on WFI when V=1
Alistair Francis
1
-2
/
+3
2020-02-27
target/ricsv: Flush the TLB on virtulisation mode changes
Alistair Francis
1
-0
/
+5
2020-02-27
target/riscv: Add support for virtual interrupt setting
Alistair Francis
1
-5
/
+28
2020-02-27
target/riscv: Extend the SIP CSR to support virtulisation
Alistair Francis
1
-1
/
+12
2020-02-27
target/riscv: Extend the MIE CSR to support virtulisation
Alistair Francis
1
-4
/
+20
2020-02-27
target/riscv: Set VS bits in mideleg for Hyp extension
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Add virtual register swapping function
Alistair Francis
3
-0
/
+79
2020-02-27
target/riscv: Add Hypervisor machine CSRs accesses
Alistair Francis
1
-0
/
+27
2020-02-27
target/riscv: Add Hypervisor virtual CSRs accesses
Alistair Francis
1
-0
/
+116
2020-02-27
target/riscv: Add Hypervisor CSR access functions
Alistair Francis
1
-2
/
+134
2020-02-27
target/riscv: Dump Hypervisor registers if enabled
Alistair Francis
1
-0
/
+33
2020-02-27
target/riscv: Print priv and virt in disas log
Alistair Francis
1
-0
/
+8
2020-02-27
target/riscv: Fix CSR perm checking for HS mode
Alistair Francis
1
-4
/
+14
2020-02-27
target/riscv: Add the force HS exception mode
Alistair Francis
3
-0
/
+26
2020-02-27
target/riscv: Add the virtulisation mode
Alistair Francis
3
-0
/
+25
2020-02-27
target/riscv: Rename the H irqs to VS irqs
Alistair Francis
2
-9
/
+9
2020-02-27
target/riscv: Add support for the new execption numbers
Alistair Francis
4
-20
/
+37
2020-02-27
target/riscv: Add the Hypervisor CSRs to CPUState
Alistair Francis
3
-18
/
+48
2020-02-27
target/riscv: Add the Hypervisor extension
Alistair Francis
1
-0
/
+1
2020-02-27
target/riscv: Convert MIP CSR to target_ulong
Alistair Francis
2
-2
/
+2
2020-02-27
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200227' into staging
Peter Maydell
7
-17
/
+64
2020-02-27
s390x: Rename and use constants for short PSW address and mask
Janosch Frank
2
-3
/
+4
2020-02-26
s390/sclp: improve special wait psw logic
Christian Borntraeger
1
-1
/
+1
2020-02-26
s390x: Add missing vcpu reset functions
Janosch Frank
4
-12
/
+58
2020-02-26
target/s390x/translate: Fix RNSBG instruction
Thomas Huth
1
-1
/
+1
2020-02-25
target/riscv: progressively load the instruction during decode
Alex Bennée
2
-23
/
+25
2020-02-25
Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD
Paolo Bonzini
7
-19
/
+18
2020-02-25
target/i386: check for empty register in FXAM
Paolo Bonzini
1
-1
/
+5
2020-02-21
target/arm: Set MVFR0.FPSP for ARMv5 cpus
Richard Henderson
1
-4
/
+6
2020-02-21
target/arm: Use isar_feature_aa32_simd_r32 more places
Richard Henderson
3
-13
/
+11
2020-02-21
target/arm: Rename isar_feature_aa32_simd_r32
Richard Henderson
2
-27
/
+28
2020-02-21
target/arm: Convert PMULL.8 to gvec
Richard Henderson
6
-55
/
+95
2020-02-21
target/arm: Convert PMULL.64 to gvec
Richard Henderson
5
-72
/
+39
2020-02-21
target/arm: Convert PMUL.8 to gvec
Richard Henderson
5
-37
/
+39
2020-02-21
target/arm: Vectorize USHL and SSHL
Richard Henderson
6
-66
/
+389
2020-02-21
target/arm: Correctly implement ACTLR2, HACTLR2
Peter Maydell
4
-9
/
+33
2020-02-21
target/arm: Use FIELD_EX32 for testing 32-bit fields
Peter Maydell
1
-9
/
+9
2020-02-21
target/arm: Use isar_feature function for testing AA32HPD feature
Peter Maydell
2
-2
/
+7
2020-02-21
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
Peter Maydell
6
-79
/
+106
2020-02-21
target/arm: Correct handling of PMCR_EL0.LC bit
Peter Maydell
1
-4
/
+9
2020-02-21
target/arm: Correct definition of PMCRDP
Peter Maydell
1
-1
/
+2
2020-02-21
target/arm: Provide ARMv8.4-PMU in '-cpu max'
Peter Maydell
1
-0
/
+8
2020-02-21
target/arm: Implement ARMv8.4-PMU extension
Peter Maydell
2
-1
/
+39
[prev]
[next]