riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-21	target/arm: Add isar_feature_any_fp16 and document naming/usage conventions	Peter Maydell	2	-2/+19
2020-02-21	target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan	Peter Maydell	1	-1/+1
2020-02-21	target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers	Peter Maydell	5	-10/+19
2020-02-21	target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid	Richard Henderson	2	-34/+37
2020-02-21	target/arm: Remove ttbr1_valid check from get_phys_addr_lpae	Richard Henderson	1	-5/+1
2020-02-21	target/arm: Fix select for aa64_va_parameters_both	Richard Henderson	1	-22/+24
2020-02-21	target/arm: Use bit 55 explicitly for pauth	Richard Henderson	1	-1/+2
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD INS	Richard Henderson	1	-0/+6
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN	Richard Henderson	1	-0/+1
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX	Richard Henderson	1	-0/+1
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD EXT	Richard Henderson	1	-0/+1
2020-02-21	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	BALATON Zoltan	1	-91/+54
2020-02-21	target/ppc/cpu.h: Move fpu related members closer in cpu env	BALATON Zoltan	1	-5/+4
2020-02-21	target/ppc: Fix typo in comments	BALATON Zoltan	2	-5/+5
2020-02-21	target/ppc/cpu.h: Remove duplicate includes	BALATON Zoltan	1	-2/+0
2020-02-18	target/i386/whpx: Remove superfluous semicolon	Philippe Mathieu-Daudé	1	-1/+1
2020-02-14	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf2' i...	Peter Maydell	1	-9/+11
2020-02-14	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200213'...	Peter Maydell	11	-118/+500
2020-02-13	target/arm: Implement ARMv8.1-VMID16 extension	Peter Maydell	1	-0/+1
2020-02-13	target/arm: Enable ARMv8.2-UAO in -cpu max	Richard Henderson	1	-0/+4
2020-02-13	target/arm: Implement UAO semantics	Richard Henderson	1	-20/+21
2020-02-13	target/arm: Update MSR access to UAO	Richard Henderson	4	-0/+44
2020-02-13	target/arm: Add ID_AA64MMFR2_EL1	Richard Henderson	3	-2/+21
2020-02-13	target/arm: Enable ARMv8.2-ATS1E1 in -cpu max	Richard Henderson	2	-0/+9
2020-02-13	target/arm: Implement ATS1E1 system registers	Richard Henderson	1	-6/+50
2020-02-13	target/arm: Set PAN bit as required on exception entry	Richard Henderson	1	-3/+50
2020-02-13	target/arm: Enforce PAN semantics in get_S1prot	Richard Henderson	2	-0/+16
2020-02-13	target/arm: Update arm_mmu_idx_el for PAN	Richard Henderson	1	-0/+9
2020-02-13	target/arm: Update MSR access for PAN	Richard Henderson	4	-0/+43
2020-02-13	target/arm: Introduce aarch64_pstate_valid_mask	Richard Henderson	2	-0/+13
2020-02-13	target/arm: Remove CPSR_RESERVED	Richard Henderson	2	-7/+8
2020-02-13	target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return	Richard Henderson	1	-2/+3
2020-02-13	target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask	Richard Henderson	2	-3/+4
2020-02-13	target/arm: Mask CPSR_J when Jazelle is not enabled	Richard Henderson	1	-1/+4
2020-02-13	target/arm: Split out aarch32_cpsr_valid_mask	Richard Henderson	2	-23/+38
2020-02-13	target/arm: Move LOR regdefs to file scope	Richard Henderson	1	-28/+29
2020-02-13	target/arm: Add isar_feature tests for PAN + ATS1E1	Richard Henderson	1	-0/+29
2020-02-13	target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled	Richard Henderson	6	-22/+87
2020-02-13	target/arm: Add arm_mmu_idx_is_stage1_of_2	Richard Henderson	2	-5/+21
2020-02-13	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	3	-6/+11
2020-02-12	target/i386: enable monitor and ucode revision with -cpu max	Paolo Bonzini	1	-0/+2
2020-02-12	target/i386: check for availability of MSR_IA32_UCODE_REV as an emulated MSR	Paolo Bonzini	1	-2/+5
2020-02-12	target/i386: fix TCG UCODE_REV access	Paolo Bonzini	1	-4/+4
2020-02-10	riscv: Separate FPU register size from core register size in gdbstub [v2]	Keith Packard	1	-9/+11
2020-02-07	target/arm: Raise only one interrupt in arm_cpu_exec_interrupt	Richard Henderson	1	-18/+12
2020-02-07	target/arm: Use bool for unmasked in arm_excp_unmasked	Richard Henderson	1	-3/+3
2020-02-07	target/arm: Pass more cpu state to arm_excp_unmasked	Richard Henderson	1	-10/+12
2020-02-07	target/arm: Move arm_excp_unmasked to cpu.c	Richard Henderson	2	-111/+119
2020-02-07	target/arm: Enable ARMv8.1-VHE in -cpu max	Richard Henderson	1	-0/+1
2020-02-07	target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE	Richard Henderson	1	-2/+7