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2019-03-29target/ppc: Fix QEMU crash with stxsdxGreg Kurz1-1/+1
2019-03-29target/ppc: Improve comment of bcctr used for spectre v2 mitigationGreg Kurz1-1/+9
2019-03-29target/ppc: Consolidate 64-bit server processor detection in a helperGreg Kurz3-7/+11
2019-03-29target/ppc: Enable "decrement and test CTR" version of bcctrGreg Kurz1-15/+37
2019-03-29target/ppc: Fix TCG temporary leaks in gen_bcond()Greg Kurz1-0/+2
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-0/+11
2019-03-28Merge remote-tracking branch 'remotes/xtensa/tags/20190326-xtensa' into stagingPeter Maydell2-2/+0
2019-03-26target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu maxRichard Henderson1-0/+5
2019-03-26target/riscv: Fix wrong expanding for c.fswspKito Cheng1-1/+1
2019-03-26Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1' i...Peter Maydell2-2/+23
2019-03-25Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell7-17/+17
2019-03-25target/arm: make pmccntr_op_start/finish staticAndrew Jones2-13/+2
2019-03-25target/arm: cortex-a7 and cortex-a15 have pmusAndrew Jones1-0/+3
2019-03-25target/arm: fix crash on pmu register accessAndrew Jones1-0/+4
2019-03-25target/arm: Fix non-parallel expansion of CASPRichard Henderson1-1/+1
2019-03-23target/xtensa: don't announce exit simcallMax Filippov1-1/+0
2019-03-22trace-events: Shorten file names in commentsMarkus Armbruster7-17/+17
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2-2/+23
2019-03-21target/xtensa: fix break_dependency for repeated resourcesMax Filippov1-1/+0
2019-03-20i386: Disable OSPKE on CPU model definitionsEduardo Habkost1-3/+3
2019-03-20i386: Make arch_capabilities migratableEduardo Habkost1-1/+0
2019-03-20i386: kvm: Disable arch_capabilities if MSR can't be setEduardo Habkost1-0/+9
2019-03-19target/riscv: Remove unused structAlistair Francis1-6/+0
2019-03-19RISC-V: Update load reservation comment in do_interruptMichael Clark1-1/+7
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark2-9/+5
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark2-97/+60
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark1-2/+2
2019-03-19RISC-V: linux-user support for RVE ABIKito Cheng2-1/+6
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark3-8/+15
2019-03-19riscv: pmp: Log pmp access errors as guest errorsAlistair Francis1-7/+13
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson3-12/+349
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson2-7/+30
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson1-2/+33
2019-03-18target/i386: sev: Do not pin the ram device memory regionSingh, Brijesh1-0/+11
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann1-5/+25
2019-03-15target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson1-14/+28
2019-03-15target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif1-8/+14
2019-03-15target/arm: change arch timer registers access permissionDongjiu Geng1-15/+15
2019-03-13Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell12-1589/+2891
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann1-20/+1
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann1-34/+0
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann3-18/+18
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2-211/+164
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2-71/+81
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann3-30/+34
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann3-100/+108
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2-11/+24
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2-16/+25
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2-60/+33
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann2-39/+27