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2022-07-06target/s390x/tcg: SPX: check validity of new prefixJanis Schoetterl-Glausch1-0/+7
According to the architecture, SET PREFIX must try to access the new prefix area and recognize an addressing exception if the area is not accessible. For qemu this check prevents a crash in cpu_map_lowcore after an inaccessible prefix area has been set. Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220630094340.3646279-1-scgl@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-05Merge tag 'pull-request-2022-07-05' of https://gitlab.com/thuth/qemu into ↵Richard Henderson1-7/+0
staging * Fix memory leak in test-cutils * Fix edk2/opensbi jobs to not run automatically by accident * Improve timings in the migration qtest * Remove libvixl disassembler * Add ukrainian translation * Require a recent version of libpng # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmLECEkRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbV7lxAAmEItM6PIoW58eWPzReKVH8LE2w3UlvOZ # JQhNgJjuN23fqjUVkcT0yCfdNCz/nKvafHnxfHQnrAXyB5V5vU8ovBgSuWK2mcmD # NTFK+/2x5lcsyBrOe3QoeD2g1r7+Os3AYVkdnN/t2HAMLwQyaoshKaMV/UHC9O/i # Kle1svYRNyCgyXJgxaOdbVMBSLi/L9h2R5AaG31GIi9wnf0n8HDH/ONtmeIpN09g # BlMeZqPhGJT+tpMvviif65/Za57Y9h/r+TOgEIIs00cWmxqaBmcXXN9qog2s0n7A # nOm3ck2lpGJCQ6+sl6/Mphyr3X6nWHsxGrLDElS0Ba5bg6T/Xqfg2pBcb81Klkjc # QcTdFPiMxKUczgpFq326sqiaVzMgys4vwnW5iPSd5swNzrkYKADAIreki5jyM3cH # lohBG/ruOmg5xMkX2K6pra0iOAeCz44Ku/HTREfY1CTUgEQZJY4SZrMJSnmUTnM+ # EQCkDcmOsnFDaQazneCbo18l37cXOgEhH8VoGAOqg1aRjr7TNlsJzx87PoD+9zNR # GEh7kp18ABRGik5ZACdLQ/HhhOJa8+UWsGCwCdeBGv/TVug1Byz0OUG0PxX3X5SV # WwubeKyZcqzoH92SQI3jZGSmuGBySy9q51T2k8FjZvaDsPiUN/MLPspNezH1qj2B # W7qEaqIyGmo= # =Q2vV # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Jul 2022 03:15:45 PM +0530 # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-05' of https://gitlab.com/thuth/qemu: include/qemu/host-utils: Remove unused code in the *_overflow wrappers meson.build: Require a recent version of libpng po: add ukrainian translation disas: Remove libvixl disassembler tests: use consistent bandwidth/downtime limits in migration tests tests: increase migration test converge downtime to 30 seconds tests: wait for migration completion before looking for STOP event tests: wait max 120 seconds for migration test status changes gitlab-ci: Extend timeout for ubuntu-20.04-s390x-all to 75m gitlab: honour QEMU_CI variable in edk2/opensbi jobs gitlab: tweak comments in edk2/opensbi jobs gitlab: normalize indentation in edk2/opensbi rules tests/fp: Do not build softfloat3 tests if TCG is disabled tests: fix test-cutils leaks Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-05target/loongarch: Clean up tlb when cpu resetSong Gao1-0/+1
We should make sure that tlb is clean when cpu reset. Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220705070950.2364243-1-gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-05disas: Remove libvixl disassemblerThomas Huth1-7/+0
The disassembly via capstone should be superiour to our old vixl sources nowadays, so let's finally cut this old disassembler out of the QEMU source tree. Message-Id: <20220603164249.112459-1-thuth@redhat.com> Tested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-04target/loongarch: Add lock when writing timer clear regXiaojuan Yang1-0/+2
There is such error info when running linux kernel: tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()). calling stack: #0 in raise () at /lib64/libc.so.6 #1 in abort () at /lib64/libc.so.6 #2 in g_assertion_message_expr.cold () at /lib64/libglib-2.0.so.0 #3 in g_assertion_message_expr () at /lib64/libglib-2.0.so.0 #4 in tcg_handle_interrupt (cpu=0x632000030800, mask=2) at ../accel/tcg/tcg-accel-ops.c:79 #5 in cpu_interrupt (cpu=0x632000030800, mask=2) at ../softmmu/cpus.c:248 #6 in loongarch_cpu_set_irq (opaque=0x632000030800, irq=11, level=0) at ../target/loongarch/cpu.c:100 #7 in helper_csrwr_ticlr (env=0x632000039440, val=1) at ../target/loongarch/csr_helper.c:85 #8 in code_gen_buffer () #9 in cpu_tb_exec (cpu=0x632000030800, itb=0x7fff946ac280, tb_exit=0x7ffe4fcb6c30) at ../accel/tcg/cpu-exec.c:358 Add mutex iothread lock around loongarch_cpu_set_irq in csrwr_ticlr() to fix the bug. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: Fix the meaning of ECFG reg's VS fieldXiaojuan Yang1-0/+4
By the manual of LoongArch CSR, the VS field(18:16 bits) of ECFG reg means that the number of instructions between each exception entry is 2^VS. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-9-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: Update READMESong Gao1-2/+37
Add linux-user emulation introduction Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-14-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: Adjust functions and structure to support user-modeSong Gao6-1/+72
Some functions and member of the structure are different with softmmu-mode So we need adjust them to support user-mode. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-12-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: remove unused include hw/loader.hSong Gao1-1/+0
Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-11-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exceptionSong Gao2-2/+4
Raise EXCCODE_BCE instead of EXCCODE_ADEM for helper_asrtle_d/asrtgt_d. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-10-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: Fix missing update CSR_BADVSong Gao1-4/+6
loongarch_cpu_do_interrupt() should update CSR_BADV for some EXCCODE. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-9-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04target/loongarch: remove badaddr from CPULoongArchSong Gao2-3/+1
We can use CSR_BADV to replace badaddr. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-8-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel2-70/+66
The latest AIA draft v0.3.0 defines a relatively simpler scheme for default priority assignments where: 1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use and have implementation specific default priority. 2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended (not mandatory) priority assignments. We update the default priority table and hviprio mapping as-per above. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2-168/+6
Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC CSR emulation as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel1-1/+1
The minimum priv spec versino for mcountinhibit to v1.11 so that it is not available for v1.10 (or lower). Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel1-4/+8
The riscv_cpu_realize() sets priv spec version to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis1-1/+1
The Ibex CPU supports version 1.11 of the priv spec [1], so let's correct that in QEMU as well. 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220629233102.275181-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis1-1/+1
There is nothing in the RISC-V spec that mandates version 1.12 is required for ePMP and there is currently hardware [1] that implements ePMP (a draft version though) with the 1.11 priv spec. 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra6-53/+213
mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra3-152/+331
With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra4-0/+32
As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra3-36/+63
The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra3-5/+5
The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM architecture as well. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra1-0/+51
Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra1-4/+7
The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre1-0/+3
For a TOR entry to match, the stard address must be lower than the end address. Normally this is always the case, but correct code might still run into the following scenario: Initial state: pmpaddr3 = 0x2000 pmp3cfg = OFF pmpaddr4 = 0x3000 pmp4cfg = TOR Execution: 1. write 0x40ff to pmpaddr3 2. write 0x32ff to pmpaddr4 3. set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0 4. set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1 When (2) is emulated, a call to pmp_update_rule() creates a negative range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated, a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return a very creatively large TLB size for pmp4. This, in turn, may result in accesses to non-existent/unitialized memory regions and a fault, so that (4) ends up never being executed. This is in m-mode with MPRV unset, meaning that unlocked PMP entries should have no effect. Therefore such a behavior based on PMP content is very unexpected. Make sure no negative PMP range can be created, whether explicitly by the emulated code or implicitly like the above. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson4-9/+17
The set of instructions that require decode_save_opc for unwinding is really fairly small -- only insns that can raise ILLEGAL_INSN at runtime. This includes CSR, anything that uses a *new* fp rounding mode, and many privileged insns. Since unwind info is stored as the difference from the previous insn, storing a 0 for most insns minimizes the size of the unwind info. Booting a debian kernel image to the missing rootfs panic yields - gen code size 22226819/1026886656 + gen code size 21601907/1026886656 on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson1-9/+2
The function doesn't set mtval, it sets badaddr. Move the set of badaddr directly into gen_exception_inst_addr_mis and use generate_exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson1-0/+2
While we set env->bins when unwinding for ILLEGAL_INST, from e.g. csrrw, we weren't setting it for immediately illegal instructions. Add a testcase for mtval via both exception paths. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2
Commit 57c108b8646 introduced gen_set_gpri(), which already contains a check for if the destination register is 'zero'. The check in auipc and lui are then redundant. This patch removes those checks. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-28target/nios2: Move nios2-semi.c to nios2_softmmu_ssRichard Henderson2-7/+2
Semihosting is not enabled for nios2-linux-user. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/nios2: Eliminate nios2_semi_is_lseekRichard Henderson1-36/+23
Reorg nios2_semi_return_* to gdb_syscall_complete_cb. Use the 32-bit version normally, and the 64-bit version for HOSTED_LSEEK. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/mips: Drop pread and pwrite syscalls from semihostingRichard Henderson1-32/+7
We don't implement it with _WIN32 hosts, and the syscalls are missing from the gdb remote file i/o interface. Since we can't implement them universally, drop them. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/mips: Add UHI errno valuesRichard Henderson1-0/+40
From the Unified Hosting Interface, MD01069 Reference Manual, version 1.1.6, 06 July 2015. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/mips: Use an exception for semihostingRichard Henderson10-21/+19
Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/m68k: Make semihosting system onlyRichard Henderson2-38/+4
While we had a call to do_m68k_semihosting in linux-user, it wasn't actually reachable. We don't include DISAS_INSN(halt) as an instruction unless system mode. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/m68k: Eliminate m68k_semi_is_fseekRichard Henderson1-32/+23
Reorg m68k_semi_return_* to gdb_syscall_complete_cb. Use the 32-bit version normally, and the 64-bit version for HOSTED_LSEEK. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28gdbstub: Adjust gdb_syscall_complete_cb declarationRichard Henderson2-12/+6
Change 'ret' to uint64_t. This resolves a FIXME in the m68k and nios2 semihosting that we've lost data. Change 'err' to int. There is nothing target-specific about the width of the errno value. Reviewed-by: Luc Michel <lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Split out common-semi-target.hRichard Henderson2-0/+112
Move the ARM and RISCV specific helpers into their own header file. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luc Michel <lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28include/exec: Move gdb_stat and gdb_timeval to gdbstub.hRichard Henderson2-54/+8
We have two copies of these structures, and require them in semihosting/ going forward. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28include/exec: Move gdb open flags to gdbstub.hRichard Henderson2-16/+0
There were 3 copies of these flags. Place them in the file with gdb_do_syscall, with which they belong. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson3-4/+4
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall. Do not modify guest registers until the syscall is complete, which in the gdbstub case is asynchronous. In the synchronous non-gdbstub case, use common_semi_set_ret to set the result. Merge set_swi_errno into common_semi_cb. Rely on the latter for combined return value / errno setting. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.hRichard Henderson3-3/+3
We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-27target/arm: Check V7VE as well as LPAE in arm_pamaxRichard Henderson1-1/+7
In machvirt_init we create a cpu but do not fully initialize it. Thus the propagation of V7VE to LPAE has not been done, and we compute the wrong value for some v7 cpus, e.g. cortex-a15. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: He Zhe <zhe.he@windriver.com> Message-id: 20220619001541.131672-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Extend arm_pamax to more than aarch64Richard Henderson1-8/+16
Move the code from hw/arm/virt.c that is supposed to handle v7 into the one function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: He Zhe <zhe.he@windriver.com> Message-id: 20220619001541.131672-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.hRichard Henderson2-36/+38
We will need these functions in translate-sme.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SVL to TB flagsRichard Henderson4-1/+21
We need SVL separate from VL for RDSVL et al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Introduce sve_vqm1_for_el_smRichard Henderson2-9/+32
When Streaming SVE mode is enabled, the size is taken from SMCR_ELx instead of ZCR_ELx. The format is shared, but the set of vector lengths is not. Further, Streaming SVE does not require any particular length to be supported. Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM to the new function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add cpu properties for SMERichard Henderson4-7/+124
Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point for bugs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220620175235.60881-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Unexport aarch64_add_*_propertiesRichard Henderson2-5/+2
These functions are not used outside cpu64.c, so make them static. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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