riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-10	target/arm: Merge regime_is_secure into get_phys_addr	Richard Henderson	2	-44/+42
2022-10-10	target/arm: Add TBFLAG_M32.SECURE	Richard Henderson	3	-2/+7
2022-10-10	target/arm: Add is_secure parameter to v7m_read_half_insn	Richard Henderson	1	-5/+4
2022-10-10	target/arm: Split out get_phys_addr_with_secure	Richard Henderson	2	-29/+55
2022-10-10	target/arm: Add is_secure parameter to regime_translation_disabled	Richard Henderson	1	-9/+11
2022-10-10	target/arm: Fix S2 disabled check in S1_ptw_translate	Richard Henderson	1	-3/+3
2022-10-10	target/arm: Add is_secure parameter to get_phys_addr_lpae	Richard Henderson	1	-10/+10
2022-10-10	target/arm: Make the final stage1+2 write to secure be unconditional	Richard Henderson	1	-11/+10
2022-10-10	target/arm: Split s2walk_secure from ipa_secure in get_phys_addr	Richard Henderson	1	-9/+9
2022-10-10	target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented	Jerome Forissier	2	-28/+31
2022-10-10	target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR	Peter Maydell	1	-1/+3
2022-10-06	monitor: expose monitor_puts to rest of code	Alex Bennée	1	-1/+1
2022-10-05	Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into staging	Stefan Hajnoczi	9	-137/+192
2022-10-05	Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	31	-107/+298
2022-10-04	target/sh4: Fix TB_FLAG_UNALIGN	Richard Henderson	4	-74/+86
2022-10-04	accel/tcg: Introduce tb_pc and log_pc	Richard Henderson	15	-19/+19
2022-10-04	hw/core: Add CPUClass.get_pc	Richard Henderson	21	-0/+183
2022-10-04	Merge tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent...	Stefan Hajnoczi	2	-16/+10
2022-10-04	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi	1	-1/+1
2022-10-03	accel/tcg: Suppress auto-invalidate in probe_access_internal	Richard Henderson	1	-4/+0
2022-10-03	accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull	Richard Henderson	3	-10/+10
2022-10-04	Drop superfluous conditionals around g_free()	Markus Armbruster	2	-16/+10
2022-10-03	Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW	Matheus Tavares Bernardino	1	-1/+1
2022-10-01	target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp <= ...	Ray Zhang	1	-1/+1
2022-09-30	Hexagon (target/hexagon) move store size tracking to translation	Taylor Simpson	3	-28/+41
2022-09-30	Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]	Taylor Simpson	4	-10/+17
2022-09-30	Hexagon (target/hexagon) add instruction attributes from archlib	Taylor Simpson	3	-98/+133
2022-09-29	target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP	Jerome Forissier	1	-1/+1
2022-09-29	target/arm: Rearrange cpu64.c so all the CPU initfns are together	Peter Maydell	1	-356/+356
2022-09-29	target/arm: Update SDCR_VALID_MASK to include SCCD	Peter Maydell	1	-1/+7
2022-09-29	target/arm: Make writes to MDCR_EL3 use PMU start/finish calls	Peter Maydell	1	-4/+14
2022-09-29	target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO	Peter Maydell	1	-6/+6
2022-09-28	Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_viv...	Stefan Hajnoczi	1	-2/+4
2022-09-27	Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ...	Stefan Hajnoczi	3	-6/+13
2022-09-27	Merge tag 'pull-request-2022-09-26' of https://gitlab.com/thuth/qemu into sta...	Stefan Hajnoczi	5	-2/+277
2022-09-27	linux-user/hppa: Dump IIR on register dump	Helge Deller	1	-2/+4
2022-09-27	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	Yang Liu	4	-15/+31
2022-09-27	target/riscv: rvv-1.0: Simplify vfwredsum code	Yang Liu	1	-46/+10
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang	2	-4/+188
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang	1	-0/+10
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang	2	-2/+70
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang	4	-3/+18
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang	1	-6/+3
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang	4	-88/+48
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang	2	-5/+12
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang	5	-67/+140
2022-09-26	target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privil...	Mark Cave-Ayland	3	-1/+8
2022-09-26	target/m68k: increase size of m68k CPU features from uint32_t to uint64_t	Mark Cave-Ayland	2	-5/+5
2022-09-27	target/riscv: Check the correct exception cause in vector GDB stub	Frank Chang	1	-2/+2
2022-09-27	target/riscv: Set the CPU resetvec directly	Alistair Francis	3	-15/+7