riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-07-06	target/xtensa: Assert that interrupt level is within bounds	Peter Maydell	1	-0/+3
2023-06-26	target: Widen pc/cs_base in cpu_get_tb_cpu_state	Anton Johansson	1	-2/+2
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé	1	-3/+3
2023-06-05	accel/tcg: Introduce translator_io_start	Richard Henderson	1	-21/+6
2023-06-05	tcg: Pass TCGHelperInfo to tcg_gen_callN	Richard Henderson	1	-0/+4
2023-05-05	target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	1	-2/+2
2023-03-13	target/xtensa: Remove `NB_MMU_MODES` define	Anton Johansson	1	-1/+0
2023-03-07	gdbstub: move register helpers into standalone include	Alex Bennée	13	-13/+13
2023-03-05	target/xtensa: Avoid tcg_const_i32	Richard Henderson	1	-3/+3
2023-03-05	target/xtensa: Split constant in bit shift	Richard Henderson	1	-4/+4
2023-03-05	target/xtensa: Use tcg_gen_subfi_i32 in translate_sll	Richard Henderson	1	-2/+2
2023-03-05	target/xtensa: Avoid tcg_const_i32 in translate_l32r	Richard Henderson	1	-3/+3
2023-03-05	target/xtensa: Tidy translate_clamps	Richard Henderson	1	-4/+4
2023-03-05	target/xtensa: Tidy translate_bb	Richard Henderson	1	-11/+7
2023-03-05	target/xtensa: Drop tcg_temp_free	Richard Henderson	1	-107/+0
2023-03-05	target/xtensa: Drop reset_sar_tracker	Richard Henderson	1	-12/+2
2023-03-01	target/xtensa: Don't use tcg_temp_local_new_*	Richard Henderson	1	-8/+8
2023-03-01	accel/tcg: Pass max_insn to gen_intermediate_code by pointer	Richard Henderson	1	-1/+1
2023-02-27	target/xtensa/cpu: Include missing "memory.h" header	Philippe Mathieu-Daudé	1	-0/+3
2023-02-27	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	Philippe Mathieu-Daudé	1	-1/+1
2022-12-16	target/xtensa: Convert to 3-phase reset	Peter Maydell	2	-6/+10
2022-11-01	accel/tcg: Remove will_exit argument from cpu_restore_state	Richard Henderson	1	-3/+3
2022-10-26	target/xtensa: Convert to tcg_ops restore_state_to_opc	Richard Henderson	2	-6/+10
2022-10-04	hw/core: Add CPUClass.get_pc	Richard Henderson	1	-0/+8
2022-09-13	target/xtensa: Honour -semihosting-config userspace=on	Peter Maydell	1	-3/+4
2022-09-13	semihosting: Allow optional use of semihosting from userspace	Peter Maydell	1	-3/+3
2022-09-06	accel/tcg: Add pc and host_pc params to gen_intermediate_code	Richard Henderson	1	-2/+4
2022-05-11	Clean up decorations and whitespace around header guards	Markus Armbruster	2	-6/+2
2022-05-11	Normalize header guard symbol definition	Markus Armbruster	1	-1/+1
2022-05-11	Clean up header guards that don't match their file name	Markus Armbruster	2	-9/+6
2022-05-06	target/xtensa: implement cache test option opcodes	Max Filippov	1	-0/+38
2022-05-06	target/xtensa: add clock input to xtensa CPU	Max Filippov	3	-3/+24
2022-05-06	target/xtensa: import core lx106	Simon Safar	5	-0/+8273
2022-05-06	target/xtensa: use tcg_constant_* for remaining opcodes	Max Filippov	1	-52/+25
2022-05-06	target/xtensa: use tcg_constant_* for FPU conversion opcodes	Max Filippov	1	-12/+6
2022-05-06	target/xtensa: use tcg_constant_* for numbered special registers	Max Filippov	1	-12/+4
2022-05-06	target/xtensa: use tcg_constant_* for TLB opcodes	Max Filippov	1	-8/+4
2022-05-06	target/xtensa: use tcg_constant_* for exceptions	Max Filippov	1	-13/+5
2022-05-06	target/xtensa: use tcg_contatnt_* for numeric literals	Max Filippov	1	-19/+9
2022-05-06	target/xtensa: fix missing tcg_temp_free in gen_window_check	Max Filippov	1	-2/+2
2022-04-21	compiler.h: replace QEMU_NORETURN with G_NORETURN	Marc-André Lureau	1	-3/+3
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson	1	-3/+4
2022-04-06	Remove qemu-common.h include from most units	Marc-André Lureau	4	-4/+0
2022-04-06	Move CPU softfloat unions to cpu-float.h	Marc-André Lureau	1	-0/+1
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau	3	-5/+5
2022-04-06	Replace config-time define HOST_WORDS_BIGENDIAN	Marc-André Lureau	1	-1/+1
2022-03-06	target: Use ArchCPU as interface to target CPU	Philippe Mathieu-Daudé	1	-1/+1
2022-03-06	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	Philippe Mathieu-Daudé	2	-4/+1
2022-03-06	target: Use CPUArchState as interface to target-specific CPU state	Philippe Mathieu-Daudé	1	-4/+3
2022-03-06	target: Use forward declared type instead of structure type	Philippe Mathieu-Daudé	1	-1/+1