Age | Commit message (Expand) | Author | Files | Lines |
2019-10-28 | target/xtensa: fetch code with translator_ld | Emilio G. Cota | 1 | -2/+2 |
2019-10-18 | target/xtensa: regenerate and re-import test_mmuhifi_c3 core | Max Filippov | 4 | -3001/+3154 |
2019-09-11 | target/xtensa: linux-user: add call0 ABI support | Max Filippov | 2 | -4/+23 |
2019-08-22 | Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in... | Peter Maydell | 1 | -1/+1 |
2019-08-21 | hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ | Markus Armbruster | 1 | -1/+1 |
2019-08-20 | icount: remove unnecessary gen_io_end calls | Pavel Dovgalyuk | 1 | -15/+0 |
2019-08-20 | configure: Define target access alignment in configure | tony.nguyen@bt.com | 1 | -2/+0 |
2019-08-16 | Clean up inclusion of sysemu/sysemu.h | Markus Armbruster | 2 | -2/+0 |
2019-07-02 | hmp: Move hmp.h to include/monitor/ | Markus Armbruster | 1 | -1/+1 |
2019-06-12 | Include qemu-common.h exactly where needed | Markus Armbruster | 7 | -7/+0 |
2019-06-12 | Include qemu/module.h where needed, drop it from qemu-common.h | Markus Armbruster | 1 | -1/+1 |
2019-06-10 | cpu: Remove CPU_COMMON | Richard Henderson | 1 | -2/+0 |
2019-06-10 | cpu: Introduce CPUNegativeOffsetState | Richard Henderson | 1 | -0/+1 |
2019-06-10 | cpu: Introduce cpu_set_cpustate_pointers | Richard Henderson | 1 | -2/+1 |
2019-06-10 | cpu: Move ENV_OFFSET to exec/gen-icount.h | Richard Henderson | 1 | -2/+0 |
2019-06-10 | target/xtensa: Use env_cpu, env_archcpu | Richard Henderson | 6 | -31/+20 |
2019-06-10 | cpu: Replace ENV_GET_CPU with env_cpu | Richard Henderson | 1 | -2/+0 |
2019-06-10 | cpu: Define ArchCPU | Richard Henderson | 1 | -0/+1 |
2019-06-10 | cpu: Define CPUArchState with typedef | Richard Henderson | 1 | -2/+2 |
2019-06-10 | tcg: Split out target/arch/cpu-param.h | Richard Henderson | 2 | -16/+26 |
2019-05-28 | semihosting: move semihosting configuration into its own directory | Alex Bennée | 2 | -2/+2 |
2019-05-21 | Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging | Peter Maydell | 8 | -1107/+2524 |
2019-05-16 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging | Peter Maydell | 3 | -18/+25 |
2019-05-15 | target/xtensa: implement exclusive access option | Max Filippov | 6 | -2/+152 |
2019-05-15 | target/xtensa: update list of exception causes | Max Filippov | 1 | -4/+5 |
2019-05-15 | target/xtensa: implement block prefetch option opcodes | Max Filippov | 1 | -0/+42 |
2019-05-14 | target/xtensa: implement DIWBUI.P opcode | Max Filippov | 3 | -0/+12 |
2019-05-13 | target/xtensa: Use tcg_gen_abs_i32 | Richard Henderson | 1 | -8/+1 |
2019-05-13 | Clean up decorations and whitespace around header guards | Markus Armbruster | 1 | -1/+1 |
2019-05-13 | target/xtensa: Clean up core-isa.h header guards | Markus Armbruster | 4 | -20/+12 |
2019-05-10 | target/xtensa: implement MPU option | Max Filippov | 6 | -1/+566 |
2019-05-10 | target/xtensa: add parity/ECC option SRs | Max Filippov | 3 | -0/+170 |
2019-05-10 | target/xtensa: define IDMA and gather/scatter IRQ types | Max Filippov | 2 | -0/+6 |
2019-05-10 | target/xtensa: make internal MMU functions static | Max Filippov | 2 | -95/+87 |
2019-05-10 | target/xtensa: get rid of centralized SR properties | Max Filippov | 3 | -1005/+1484 |
2019-05-10 | tcg: Use CPUClass::tlb_fill in cputlb.c | Richard Henderson | 1 | -6/+0 |
2019-05-10 | target/xtensa: Convert to CPUClass::tlb_fill | Richard Henderson | 3 | -18/+31 |
2019-04-24 | tcg: Hoist max_insns computation to tb_gen_code | Richard Henderson | 1 | -2/+2 |
2019-04-18 | qom/cpu: Simplify how CPUClass:cpu_dump_state() prints | Markus Armbruster | 2 | -21/+22 |
2019-04-18 | target: Clean up how the dump_mmu() print | Markus Armbruster | 3 | -15/+13 |
2019-04-18 | target: Simplify how the TARGET_cpu_list() print | Markus Armbruster | 2 | -4/+5 |
2019-03-23 | target/xtensa: don't announce exit simcall | Max Filippov | 1 | -1/+0 |
2019-03-21 | target/xtensa: fix break_dependency for repeated resources | Max Filippov | 1 | -1/+0 |
2019-02-28 | target/xtensa: implement PREFCTL SR | Max Filippov | 2 | -0/+17 |
2019-02-28 | target/xtensa: prioritize load/store in FLIX bundles | Max Filippov | 2 | -5/+36 |
2019-02-28 | target/xtensa: break circular register dependencies | Max Filippov | 1 | -4/+123 |
2019-02-28 | target/xtensa: reorganize access to boolean registers | Max Filippov | 1 | -8/+42 |
2019-02-28 | target/xtensa: reorganize access to MAC16 registers | Max Filippov | 1 | -94/+92 |
2019-02-28 | target/xtensa: reorganize register handling in translators | Max Filippov | 3 | -344/+386 |
2019-02-28 | target/xtensa: only rotate window in the retw helper | Max Filippov | 3 | -9/+10 |