aboutsummaryrefslogtreecommitdiff
path: root/target/xtensa
AgeCommit message (Collapse)AuthorFilesLines
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé1-2/+1
Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908112235.75914-3-philmd@linaro.org>
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2-23/+18
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-13-philmd@linaro.org>
2023-11-07target/xtensa: Use env_archcpu() in update_c[compare|count]()Philippe Mathieu-Daudé1-2/+2
When CPUArchState* is available (here CPUXtensaState*), we can use the fast env_archcpu() macro to get ArchCPU* (here XtensaCPU*). The QOM cast XTENSA_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20231009110239.66778-5-philmd@linaro.org>
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2-3/+4
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-7-philmd@linaro.org>
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé2-4/+0
Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-10-22target/xtensa: Use tcg_gen_sextract_i32Richard Henderson1-11/+1
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-07meson: Rename target_softmmu_arch -> target_system_archPhilippe Mathieu-Daudé1-1/+1
Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the target_system_arch[] source set :) Mechanical change doing: $ sed -i -e s/target_softmmu_arch/target_system_arch/g \ $(git grep -l target_softmmu_arch) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-13-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-04accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson1-1/+0
This function is now empty, so remove it. In the case of m68k and tricore, this empties the class instance initfn, so remove those as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-2/+2
Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-94/+94
Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson1-2/+1
Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-03target/*: Add instance_align to all cpu base classesRichard Henderson1-0/+1
The omission of alignment has technically been wrong since 269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-31target/xtensa: Include missing 'qemu/atomic.h' headerPhilippe Mathieu-Daudé2-0/+2
Since commit fa92bd4af7 ("target/xtensa: fix access to the INTERRUPT SR") these files use QEMU atomic API. Explicit the header inclusion instead of relying on implicit and indirect inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-10-philmd@linaro.org>
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé5-5/+0
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-8-philmd@linaro.org>
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2-2/+0
These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230828221314.18435-7-philmd@linaro.org>
2023-07-06target/xtensa: Assert that interrupt level is within boundsPeter Maydell1-0/+3
In handle_interrupt() we use level as an index into the interrupt_vector[] array. This is safe because we have checked it against env->config->nlevel, but Coverity can't see that (and it is only true because each CPU config sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it complains about a possible array overrun (CID 1507131) Add an assert() which will make Coverity happy and catch the unlikely case of a mis-set XCHAL_NUM_INTLEVELS in future. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230621135633.1649-4-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-3/+3
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-21/+6
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+4
In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*Richard Henderson1-2/+2
Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20230502135741.1158035-9-richard.henderson@linaro.org>
2023-03-13target/xtensa: Remove `NB_MMU_MODES` defineAnton Johansson1-1/+0
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-23-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée13-13/+13
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
2023-03-05target/xtensa: Avoid tcg_const_i32Richard Henderson1-3/+3
All remaining uses are strictly read-only. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Split constant in bit shiftRichard Henderson1-4/+4
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Use tcg_gen_subfi_i32 in translate_sllRichard Henderson1-2/+2
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Avoid tcg_const_i32 in translate_l32rRichard Henderson1-3/+3
Use addi on the addition side and tcg_constant_i32 on the other. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Tidy translate_clampsRichard Henderson1-4/+4
All writes to arg[0].out; use tcg_constant_i32. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Tidy translate_bbRichard Henderson1-11/+7
Replace ifdefs with C, tcg_const_i32 with tcg_constant_i32. We only need a single temporary for this. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Drop tcg_temp_freeRichard Henderson1-107/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/xtensa: Drop reset_sar_trackerRichard Henderson1-12/+2
Translators are no longer required to free tcg temporaries. Remove sar_m32_allocated, as sar_m32 non-null is equivalent. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01target/xtensa: Don't use tcg_temp_local_new_*Richard Henderson1-8/+8
Since tcg_temp_new_* is now identical, use those. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-27target/xtensa/cpu: Include missing "memory.h" headerPhilippe Mathieu-Daudé1-0/+3
Under system emulation, xtensa_cpu_initfn() calls memory_region_init_io(), itself declared in "exec/memory.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221217172907.8364-10-philmd@linaro.org>
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
The 'hwaddr' type is only available / meaningful on system emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-5-philmd@linaro.org>
2022-12-16target/xtensa: Convert to 3-phase resetPeter Maydell2-6/+10
Convert the xtensa CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-20-peter.maydell@linaro.org
2022-11-01accel/tcg: Remove will_exit argument from cpu_restore_stateRichard Henderson1-3/+3
The value passed is always true, and if the target's synchronize_from_tb hook is non-trivial, not exiting may be erroneous. Reviewed-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-26target/xtensa: Convert to tcg_ops restore_state_to_opcRichard Henderson2-6/+10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson1-0/+8
Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core) Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core) Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core) Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs) Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs) Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs) Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs) Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs) Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
2022-09-13target/xtensa: Honour -semihosting-config userspace=onPeter Maydell1-3/+4
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. xtensa semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-7-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13semihosting: Allow optional use of semihosting from userspacePeter Maydell1-3/+3
Currently our semihosting implementations generally prohibit use of semihosting calls in system emulation from the guest userspace. This is a very long standing behaviour justified originally "to provide some semblance of security" (since code with access to the semihosting ABI can do things like read and write arbitrary files on the host system). However, it is sometimes useful to be able to run trusted guest code which performs semihosting calls from guest userspace, notably for test code. Add a command line suboption to the existing semihosting-config option group so that you can explicitly opt in to semihosting from guest userspace with -semihosting-config userspace=on (There is no equivalent option for the user-mode emulator, because there by definition all code runs in userspace and has access to semihosting already.) This commit adds the infrastructure for the command line option and adds a bool 'is_user' parameter to the function semihosting_userspace_enabled() that target code can use to check whether it should be permitting the semihosting call for userspace. It mechanically makes all the callsites pass 'false', so they continue checking "is semihosting enabled in general". Subsequent commits will make each target that implements semihosting honour the userspace=on option by passing the correct value and removing whatever "don't do this for userspace" checking they were doing by hand. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-2-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+4
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-11Clean up decorations and whitespace around header guardsMarkus Armbruster2-6/+2
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-11Normalize header guard symbol definitionMarkus Armbruster1-1/+1
We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster2-9/+6
Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-2-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [Change to generated file ebpf/rss.bpf.skeleton.h backed out]
2022-05-06target/xtensa: implement cache test option opcodesMax Filippov1-0/+38
We don't model caches, so for l*ct opcodes return tags with all bits (including Valid) set to 0. For all other opcodes don't do anything. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06target/xtensa: add clock input to xtensa CPUMax Filippov3-3/+24
Create clock input for the xtensa CPU device and initialize its frequency to the default core frequency specified in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06target/xtensa: import core lx106Simon Safar5-0/+8273
This is the core used in e.g. ESP8266 chips. Importing them using import_core.sh, with the required files sourced from https://github.com/espressif/xtensa-overlays core-lx106.c was generated by the script; the only change is removing the reference to core-matmap.h which doesn't seem to be available. Signed-off-by: Simon Safar <simon@simonsafar.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20220423040835.29254-1-simon@simonsafar.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov1-52/+25
- gen_jumpi passes target PC to the helper; - gen_callw_slot uses callinc (1..3); - gen_brcondi passes immediate field (less than 32 different possible values) to the helper; - disas_xtensa_insn passes PC to the helpers; - translate_entry passes PC, stack register number (0..15) and stack frame size to the helper; - gen_check_exclusive passes PC and boolean flag to the helper; - test_exceptions_retw passes PC to the helper; - gen_check_atomctl passes PC to the helper; - translate_ssai passes immediate shift amount (0..31) to the helper; - gen_waiti passes next PC and an immediate (0..15) to the helper; use tcg_constant_* for the constants listed above. Fold gen_waiti body into the translate_waiti as it's the only user. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov1-12/+6
FPU conversion opcodes pass scale (range 0..15) and rounding mode to their helpers. Use tcg_constant_* for them. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
generated by cgit v1.1 at 2024-11-20 09:36:15 +0000