riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-06	target/xtensa: use tcg_constant_* for numbered special registers	Max Filippov	1	-12/+4
2022-05-06	target/xtensa: use tcg_constant_* for TLB opcodes	Max Filippov	1	-8/+4
2022-05-06	target/xtensa: use tcg_constant_* for exceptions	Max Filippov	1	-13/+5
2022-05-06	target/xtensa: use tcg_contatnt_* for numeric literals	Max Filippov	1	-19/+9
2022-05-06	target/xtensa: fix missing tcg_temp_free in gen_window_check	Max Filippov	1	-2/+2
2022-04-21	compiler.h: replace QEMU_NORETURN with G_NORETURN	Marc-André Lureau	1	-3/+3
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson	1	-3/+4
2022-04-06	Remove qemu-common.h include from most units	Marc-André Lureau	4	-4/+0
2022-04-06	Move CPU softfloat unions to cpu-float.h	Marc-André Lureau	1	-0/+1
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau	3	-5/+5
2022-04-06	Replace config-time define HOST_WORDS_BIGENDIAN	Marc-André Lureau	1	-1/+1
2022-03-06	target: Use ArchCPU as interface to target CPU	Philippe Mathieu-Daudé	1	-1/+1
2022-03-06	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	Philippe Mathieu-Daudé	2	-4/+1
2022-03-06	target: Use CPUArchState as interface to target-specific CPU state	Philippe Mathieu-Daudé	1	-4/+3
2022-03-06	target: Use forward declared type instead of structure type	Philippe Mathieu-Daudé	1	-1/+1
2022-02-21	exec/exec-all: Move 'qemu/log.h' include in units requiring it	Philippe Mathieu-Daudé	6	-0/+6
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot	1	-2/+2
2021-11-03	Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...	Richard Henderson	1	-1/+1
2021-11-02	target/xtensa: Make xtensa_cpu_tlb_fill sysemu only	Richard Henderson	3	-23/+3
2021-10-31	monitor: Trim some trailing space from human-readable output	Markus Armbruster	1	-1/+1
2021-10-15	target/xtensa: Drop check for singlestep_enabled	Richard Henderson	1	-17/+8
2021-10-05	target/xtensa: list cores in a text file	Paolo Bonzini	3	-2/+14
2021-09-21	hw/core: Make do_unaligned_access noreturn	Richard Henderson	1	-2/+2
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-2/+0
2021-09-14	target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	3	-8/+5
2021-09-14	target/xtensa: Restrict do_transaction_failed() to sysemu	Philippe Mathieu-Daudé	1	-0/+2
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich	1	-2/+3
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson	1	-17/+0
2021-07-12	Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...	Peter Maydell	1	-6/+1
2021-07-11	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	1	-0/+2
2021-07-09	target/xtensa/xtensa-semi: Fix compilation problem on Haiku	Thomas Huth	1	-45/+39
2021-07-09	target/xtensa: Use translator_use_goto_tb	Richard Henderson	1	-5/+1
2021-07-09	tcg: Avoid including 'trace-tcg.h' in target translate.c	Philippe Mathieu-Daudé	1	-1/+0
2021-07-09	meson: Introduce target-specific Kconfig	Philippe Mathieu-Daudé	1	-0/+2
2021-05-26	hw/core: Constify TCGCPUOps	Richard Henderson	1	-1/+1
2021-05-26	cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
2021-05-26	cpu: Introduce SysemuCPUOps structure	Philippe Mathieu-Daudé	1	-0/+6
2021-05-26	cpu: Assert DeviceClass::vmsd is NULL on user emulation	Philippe Mathieu-Daudé	1	-1/+3
2021-05-20	target/xtensa: clean up unaligned access	Max Filippov	2	-66/+67
2021-05-20	target/xtensa: fix access ring in l32ex	Max Filippov	1	-1/+1
2021-05-20	target/xtensa: don't generate extra EXCP_DEBUG on exception	Max Filippov	4	-19/+0
2021-05-20	target/xtensa: Make sure that tb->size != 0	Ilya Leoshkevich	1	-0/+3
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth	1	-1/+0
2021-04-03	target/xtensa: make xtensa_modules static on import	Max Filippov	1	-0/+1
2021-04-03	target/xtensa: fix meson.build rule for xtensa cores	Max Filippov	2	-12/+4
2021-03-10	semihosting: Move include/hw/semihosting/ -> include/semihosting/	Philippe Mathieu-Daudé	2	-2/+2
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana	1	-7/+16
2021-02-05	cpu: move do_unaligned_access to tcg_ops	Claudio Fontana	1	-1/+1
2021-02-05	cpu: move cc->transaction_failed to tcg_ops	Claudio Fontana	2	-3/+3
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana	1	-1/+1