riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	3	-2/+6
2017-10-27	xtensa: cleanup cpu type name composition	Igor Mammedov	3	-2/+6
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-3/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-14/+14
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-6/+1
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-4/+0
2017-09-26	target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macro	Alistair Francis	1	-2/+2
2017-09-06	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova	1	-0/+4
2017-09-01	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	3	-25/+4
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-14	char: add backend hotswap handler	Anton Nefedov	1	-1/+1
2017-07-11	target/xtensa: gdbstub: drop dead return statement	Max Filippov	1	-1/+0
2017-06-06	target/xtensa: handle unknown registers in gdbstub	Max Filippov	1	-3/+10
2017-06-06	target/xtensa: support output to chardev console	Max Filippov	2	-14/+53
2017-06-06	target/xtensa: fix return value of read/write simcalls	Max Filippov	1	-5/+20
2017-06-06	target/xtensa: fix mapping direction in read/write simcalls	Max Filippov	1	-2/+2
2017-03-18	Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into staging	Peter Maydell	1	-13/+36
2017-03-11	target/xtensa: fix semihosting argc/argv implementation	Max Filippov	1	-13/+36
2017-03-09	target/xtensa: hold BQL for interrupt processing	Alex Bennée	2	-0/+8
2017-02-23	target/xtensa: add two missing headers to core import script	Max Filippov	1	-0/+2
2017-02-23	target/xtensa: sim: instantiate local memories	Max Filippov	2	-0/+176
2017-02-21	monitor: Fix crashes when using HMP commands without CPU	Thomas Huth	1	-0/+4
2017-01-25	Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging	Peter Maydell	7	-101/+348
2017-01-16	target-xtensa: implement RER/WER instructions	Max Filippov	6	-3/+44
2017-01-15	target/xtensa: implement MEMCTL SR	Max Filippov	6	-0/+68
2017-01-15	target/xtensa: fix ICACHE/DCACHE options detection	Max Filippov	1	-2/+2
2017-01-15	target/xtensa: don't continue translation after exception	Max Filippov	1	-1/+4
2017-01-15	target/xtensa: support icount	Max Filippov	3	-45/+143
2017-01-15	target/xtensa: refactor CCOUNT/CCOMPARE	Max Filippov	4	-46/+51
2017-01-15	target/xtensa: implement RUNSTALL	Max Filippov	3	-2/+17
2017-01-15	target/xtensa: add static vectors selection	Max Filippov	3	-3/+20
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2017-01-10	target-xtensa: Use clrsb helper	Richard Henderson	1	-10/+1
2017-01-10	target-xtensa: Use clz opcode	Richard Henderson	3	-17/+11
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	21	-0/+8786