riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	2	-1/+1
2018-02-09	Clean up includes	Markus Armbruster	6	-3/+6
2018-02-09	Use #include "..." for our own headers, <...> for others	Markus Armbruster	6	-6/+6
2018-02-05	qdev: use device_class_set_parent_realize/unrealize/reset()	Philippe Mathieu-Daudé	1	-2/+2
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-2/+2
2018-01-24	Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging	Peter Maydell	12	-7/+27668
2018-01-22	target/xtensa: disas/xtensa: fix coverity warnings	Max Filippov	1	-2/+2
2018-01-22	target/xtensa: add sample_controller core	Max Filippov	5	-0/+12216
2018-01-22	target/xtensa: allow different default CPU for MMU/noMMU	Max Filippov	1	-1/+6
2018-01-12	target/xtensa: Remove duplicate typedef of DisasContext	Peter Maydell	1	-2/+2
2018-01-11	target/xtensa: add de212 core	Max Filippov	5	-0/+15440
2018-01-11	target/xtensa: fix default sysrom/sysram addresses	Max Filippov	1	-4/+4
2018-01-09	target/xtensa: implement disassembler	Max Filippov	1	-0/+9
2018-01-09	target/xtensa: implement const16	Max Filippov	1	-0/+14
2018-01-09	target/xtensa: implement GPIO32	Max Filippov	2	-0/+54
2018-01-09	target/xtensa: implement salt/saltu	Max Filippov	1	-0/+18
2018-01-09	target/xtensa: add internal/noop SRs and opcodes	Max Filippov	2	-0/+35
2018-01-09	target/xtensa: drop DisasContext::litbase	Max Filippov	1	-22/+5
2018-01-09	target/xtensa: use libisa for instruction decoding	Max Filippov	3	-2144/+124
2017-12-18	target/xtensa: switch fsf to libisa	Max Filippov	2	-0/+9846
2017-12-18	target/xtensa: switch dc233c to libisa	Max Filippov	2	-0/+15236
2017-12-18	target/xtensa: switch dc232b to libisa	Max Filippov	2	-0/+14109
2017-12-18	target/xtensa: update import_core.sh script for libisa	Max Filippov	1	-0/+15
2017-12-18	target/xtensa: extract FPU2000 opcode translators	Max Filippov	2	-0/+375
2017-12-18	target/xtensa: extract core opcode translators	Max Filippov	2	-0/+3145
2017-12-18	target/xtensa: import libisa source	Max Filippov	4	-0/+1978
2017-12-18	target/xtensa: pass actual frame size to the entry helper	Max Filippov	2	-2/+2
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	3	-2/+6
2017-10-27	xtensa: cleanup cpu type name composition	Igor Mammedov	3	-2/+6
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-3/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-14/+14
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-6/+1
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-4/+0
2017-09-26	target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macro	Alistair Francis	1	-2/+2
2017-09-06	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova	1	-0/+4
2017-09-01	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	3	-25/+4
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-14	char: add backend hotswap handler	Anton Nefedov	1	-1/+1
2017-07-11	target/xtensa: gdbstub: drop dead return statement	Max Filippov	1	-1/+0
2017-06-06	target/xtensa: handle unknown registers in gdbstub	Max Filippov	1	-3/+10
2017-06-06	target/xtensa: support output to chardev console	Max Filippov	2	-14/+53
2017-06-06	target/xtensa: fix return value of read/write simcalls	Max Filippov	1	-5/+20
2017-06-06	target/xtensa: fix mapping direction in read/write simcalls	Max Filippov	1	-2/+2
2017-03-18	Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into staging	Peter Maydell	1	-13/+36
2017-03-11	target/xtensa: fix semihosting argc/argv implementation	Max Filippov	1	-13/+36
2017-03-09	target/xtensa: hold BQL for interrupt processing	Alex Bennée	2	-0/+8
2017-02-23	target/xtensa: add two missing headers to core import script	Max Filippov	1	-0/+2