index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
xtensa
Age
Commit message (
Expand
)
Author
Files
Lines
2021-05-26
hw/core: Constify TCGCPUOps
Richard Henderson
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Introduce SysemuCPUOps structure
Philippe Mathieu-Daudé
1
-0
/
+6
2021-05-26
cpu: Assert DeviceClass::vmsd is NULL on user emulation
Philippe Mathieu-Daudé
1
-1
/
+3
2021-05-20
target/xtensa: clean up unaligned access
Max Filippov
2
-66
/
+67
2021-05-20
target/xtensa: fix access ring in l32ex
Max Filippov
1
-1
/
+1
2021-05-20
target/xtensa: don't generate extra EXCP_DEBUG on exception
Max Filippov
4
-19
/
+0
2021-05-20
target/xtensa: Make sure that tb->size != 0
Ilya Leoshkevich
1
-0
/
+3
2021-05-02
Do not include exec/address-spaces.h if it's not really necessary
Thomas Huth
1
-1
/
+0
2021-04-03
target/xtensa: make xtensa_modules static on import
Max Filippov
1
-0
/
+1
2021-04-03
target/xtensa: fix meson.build rule for xtensa cores
Max Filippov
2
-12
/
+4
2021-03-10
semihosting: Move include/hw/semihosting/ -> include/semihosting/
Philippe Mathieu-Daudé
2
-2
/
+2
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
1
-7
/
+16
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
2
-3
/
+3
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: Move debug_excp_handler to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
1
-1
/
+1
2020-11-15
xtensa tcg cpus: Fix Lesser GPL version number
Chetan Pant
1
-1
/
+1
2020-11-13
hmp: Pass monitor to mon_get_cpu_env()
Kevin Wolf
1
-1
/
+1
2020-10-26
target/xtensa: enable all coprocessors for linux-user
Max Filippov
1
-0
/
+1
2020-09-23
qemu/atomic.h: rename atomic_ to qatomic_
Stefan Hajnoczi
2
-3
/
+3
2020-09-18
qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
Eduardo Habkost
1
-1
/
+1
2020-09-09
Use OBJECT_DECLARE_TYPE where possible
Eduardo Habkost
1
-4
/
+2
2020-09-09
Use DECLARE_*CHECKER* macros
Eduardo Habkost
1
-6
/
+2
2020-09-09
Move QOM typedefs and add missing includes
Eduardo Habkost
1
-3
/
+5
2020-08-21
target/xtensa: import DSP3400 core
Max Filippov
6
-0
/
+173129
2020-08-21
target/xtensa: import de233_fpu core
Max Filippov
6
-0
/
+22538
2020-08-21
target/xtensa: implement FPU division and square root
Max Filippov
3
-0
/
+132
2020-08-21
target/xtensa: add DFPU registers and opcodes
Max Filippov
6
-34
/
+1413
2020-08-21
target/xtensa: add DFPU option
Max Filippov
2
-0
/
+25
2020-08-21
target/xtensa: don't access BR regfile directly
Max Filippov
3
-34
/
+42
2020-08-21
target/xtensa: move FSR/FCR register accessors
Max Filippov
1
-32
/
+32
2020-08-21
target/xtensa: rename FPU2000 translators and helpers
Max Filippov
3
-55
/
+57
2020-08-21
target/xtensa: support copying registers up to 64 bits wide
Max Filippov
2
-5
/
+22
2020-08-21
target/xtensa: add geometry to xtensa_get_regfile_by_name
Max Filippov
3
-10
/
+31
2020-08-21
target/xtensa: implement NMI support
Max Filippov
3
-9
/
+21
2020-08-21
target/xtensa: make opcode properties more dynamic
Max Filippov
2
-265
/
+278
2020-08-21
meson: target
Paolo Bonzini
2
-16
/
+30
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini
21
-17
/
+17
2020-06-25
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging
Peter Maydell
3
-23
/
+46
2020-06-22
target/xtensa: drop gen_io_end call
Max Filippov
1
-3
/
+0
2020-05-19
softfloat: Name compare relation enum
Richard Henderson
1
-3
/
+3
2020-05-17
target/xtensa: fix simcall for newer hardware
Max Filippov
1
-3
/
+6
2020-05-17
target/xtensa: fetch HW version from configuration overlay
Max Filippov
2
-3
/
+6
2020-04-30
target/xtensa: work around missing SR definitions
Max Filippov
1
-14
/
+34
2020-04-15
gdbstub: Do not use memset() on GByteArray
Philippe Mathieu-Daudé
1
-4
/
+2
2020-04-07
target/xtensa: statically allocate xtensa_insnbufs in DisasContext
Max Filippov
3
-16
/
+6
[next]