riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	1	-2/+0
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-2/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	2	-16/+26
2019-05-28	semihosting: move semihosting configuration into its own directory	Alex Bennée	2	-2/+2
2019-05-21	Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging	Peter Maydell	8	-1107/+2524
2019-05-16	Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging	Peter Maydell	3	-18/+25
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov	6	-2/+152
2019-05-15	target/xtensa: update list of exception causes	Max Filippov	1	-4/+5
2019-05-15	target/xtensa: implement block prefetch option opcodes	Max Filippov	1	-0/+42
2019-05-14	target/xtensa: implement DIWBUI.P opcode	Max Filippov	3	-0/+12
2019-05-13	target/xtensa: Use tcg_gen_abs_i32	Richard Henderson	1	-8/+1
2019-05-13	Clean up decorations and whitespace around header guards	Markus Armbruster	1	-1/+1
2019-05-13	target/xtensa: Clean up core-isa.h header guards	Markus Armbruster	4	-20/+12
2019-05-10	target/xtensa: implement MPU option	Max Filippov	6	-1/+566
2019-05-10	target/xtensa: add parity/ECC option SRs	Max Filippov	3	-0/+170
2019-05-10	target/xtensa: define IDMA and gather/scatter IRQ types	Max Filippov	2	-0/+6
2019-05-10	target/xtensa: make internal MMU functions static	Max Filippov	2	-95/+87
2019-05-10	target/xtensa: get rid of centralized SR properties	Max Filippov	3	-1005/+1484
2019-05-10	tcg: Use CPUClass::tlb_fill in cputlb.c	Richard Henderson	1	-6/+0
2019-05-10	target/xtensa: Convert to CPUClass::tlb_fill	Richard Henderson	3	-18/+31
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	1	-2/+2
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	2	-21/+22
2019-04-18	target: Clean up how the dump_mmu() print	Markus Armbruster	3	-15/+13
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	2	-4/+5
2019-03-23	target/xtensa: don't announce exit simcall	Max Filippov	1	-1/+0
2019-03-21	target/xtensa: fix break_dependency for repeated resources	Max Filippov	1	-1/+0
2019-02-28	target/xtensa: implement PREFCTL SR	Max Filippov	2	-0/+17
2019-02-28	target/xtensa: prioritize load/store in FLIX bundles	Max Filippov	2	-5/+36
2019-02-28	target/xtensa: break circular register dependencies	Max Filippov	1	-4/+123
2019-02-28	target/xtensa: reorganize access to boolean registers	Max Filippov	1	-8/+42
2019-02-28	target/xtensa: reorganize access to MAC16 registers	Max Filippov	1	-94/+92
2019-02-28	target/xtensa: reorganize register handling in translators	Max Filippov	3	-344/+386
2019-02-28	target/xtensa: only rotate window in the retw helper	Max Filippov	3	-9/+10
2019-02-28	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	4	-20/+28
2019-02-28	target/xtensa: add generic instruction post-processing	Max Filippov	2	-8/+33
2019-02-28	target/xtensa: sort FLIX instruction opcodes	Max Filippov	2	-8/+221
2019-02-18	target/xtensa: implement wide branches and loops	Max Filippov	1	-27/+102
2019-02-18	target/xtensa: allow multiple names for single opcode	Max Filippov	3	-60/+60
2019-02-18	target/xtensa: don't require opcode table sorting	Max Filippov	3	-16/+42
2019-02-18	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	3	-19/+19
2019-02-18	target/xtensa: fixup test_mmuhifi_c3 overlay	Max Filippov	1	-661/+661
2019-02-11	target/xtensa: get rid of gen_callw[i]	Max Filippov	1	-21/+14
2019-02-10	target/xtensa: don't specify windowed registers manually	Max Filippov	3	-484/+12
2019-02-08	target/xtensa/import_core.sh: don't add duplicate 'static'	Max Filippov	1	-1/+1
2019-01-28	target/xtensa: add test_mmuhifi_c3 core	Max Filippov	5	-0/+36981
2019-01-28	target/xtensa: expose core runstall as an IRQ line	Max Filippov	1	-0/+2
2019-01-28	target/xtensa: rearrange access to external interrupts	Max Filippov	1	-2/+3
2019-01-28	target/xtensa: drop function xtensa_timer_irq	Max Filippov	1	-1/+0
2019-01-24	target/xtensa: fix access to the INTERRUPT SR	Max Filippov	4	-12/+19