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2017-06-06target/xtensa: handle unknown registers in gdbstubMax Filippov1-3/+10
Xtensa cores may have registers of types/sizes not supported by the gdbstub accessors. Ignore writes to such registers and return zero on read, but always return correct register size, so that gdb on the other side is able to access all registers in the packet holding unsupported registers in the middle. This fixes gdb interaction with cores that have vector/custom TIE registers. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: support output to chardev consoleMax Filippov2-14/+53
In semihosting mode QEMU allows guest to read and write host file descriptors directly, including descriptors 0..2, a.k.a. stdin, stdout and stderr. Sometimes it's desirable to have semihosting console controlled by -serial option, e.g. to connect it to network. Add semihosting console to xtensa-semi.c, open it in the 'sim' machine in the presence of -serial option and direct stdout and stderr to it when it's present. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: fix return value of read/write simcallsMax Filippov1-5/+20
Return value of read/write simcalls is not calculated correctly in case of operations crossing page boundary and in case of short reads/writes. Read and write simcalls should return the size of data actually read/written or -1 in case of error. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: fix mapping direction in read/write simcallsMax Filippov1-2/+2
Read and write simcalls map physical memory to access I/O buffers, but 'read' simcall need to map it for writing and 'write' simcall need to map it for reading, i.e. the opposite of what they do now. Fix that. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-03-18Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into stagingPeter Maydell1-13/+36
target/xtensa fixes for 2.9: - fix build failure when FDT support is not enabled; - correctly pass command line arguments to semihosting guests. # gpg: Signature made Fri 17 Mar 2017 18:14:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170317-xtensa: target/xtensa: fix semihosting argc/argv implementation target/xtensa: xtfpga: load DTB only when FDT support is enabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-11target/xtensa: fix semihosting argc/argv implementationMax Filippov1-13/+36
So far xtensa provides fixed dummy argc/argv for the corresponding semihosting calls. Now that there are semihosting_get_argc and semihosting_get_arg, use them to pass actual command line arguments to guest. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-03-09target/xtensa: hold BQL for interrupt processingAlex Bennée2-0/+8
Make sure we have the BQL held when processing interrupts. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-23target/xtensa: add two missing headers to core import scriptMax Filippov1-0/+2
Include qemu/osdep.h and qemu-common.h at the beginning of imported xtensa core source file. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-23target/xtensa: sim: instantiate local memoriesMax Filippov2-0/+176
Xtensa core may have a number of RAM and ROM areas configured. Record their size and location from the core configuration overlay and instantiate them as RAM regions in the SIM machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth1-0/+4
When running certain HMP commands ("info registers", "info cpustats", "info tlb", "nmi", "memsave" or dumping virtual memory) with the "none" machine, QEMU crashes with a segmentation fault. This happens because the "none" machine does not have any CPUs by default, but these HMP commands did not check for a valid CPU pointer yet. Add such checks now, so we get an error message about the missing CPU instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1484309555-1935-1-git-send-email-thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-01-25Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell7-101/+348
target/xtensa updates: - refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting); - support icount; run target/xtensa TCG tests with icount; - implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER. # gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170124-xtensa: target-xtensa: implement RER/WER instructions target/xtensa: tests: clean up interrupt tests target/xtensa: tests: add memctl test target/xtensa: implement MEMCTL SR target/xtensa: fix ICACHE/DCACHE options detection target/xtensa: tests: add ccount write tests target/xtensa: tests: replace hardcoded interrupt masks target/xtensa: tests: fix timer tests target/xtensa: tests: run tests with icount target/xtensa: don't continue translation after exception target/xtensa: support icount target/xtensa: refactor CCOUNT/CCOMPARE target/xtensa: implement RUNSTALL target/xtensa: add static vectors selection Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov6-3/+44
RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov6-0/+68
MEMCTL SR controls zero overhead loop buffer and number of ways enabled in L1 caches. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov1-2/+2
Configuration overlay does not explicitly say whether there are ICACHE and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect if corresponding cache option is enabled, but that's not correct: on cores without cache these macros are defined as 1, not as 0. Check XCHAL_[ID]CACHE_SIZE instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: don't continue translation after exceptionMax Filippov1-1/+4
There's no point in continuing translating guest instructions once an unconditional exception is thrown. There's also no point in updating pc before any instruction is translated, don't do it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: support icountMax Filippov3-45/+143
Delimit each instruction that may access timers or IRQ state with qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with -icount option. Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec recalculate how long this CPU is allowed to run. RSR now may need to terminate TB, but it can't be done in RSR handler because the same handler is used for XSR together with WSR handler, which may also need to terminate TB. Change RSR and WSR handlers return type to bool indicating whether TB termination is needed (RSR) or has been done (WSR), and add TB termination after RSR/WSR dispatcher call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov4-46/+51
Xtensa cores may have a register (CCOUNT) that counts core clock cycles. It may also have a number of registers (CCOMPAREx); when CCOUNT value passes the value of CCOMPAREx, timer interrupt x is raised. Currently xtensa target counts a number of completed instructions and assumes that for CCOUNT one instruction takes one cycle to complete. It calls helper function to update CCOUNT register at every TB end and raise timer interrupts. This scheme works very predictably and doesn't have noticeable performance impact, but it is hard to use with multiple synchronized processors, especially with coming MTTCG. Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL. Use native QEMU timers for CCOMPARE timers, one timer for each register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: implement RUNSTALLMax Filippov3-2/+17
RUNSTALL signal stalls core execution while it's applied. It is widely used in multicore configurations to control activity of additional cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: add static vectors selectionMax Filippov3-3/+20
Xtensa cores may have two distinct addresses for the static vectors group. Provide a function to select one of them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée1-1/+1
We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-10target-xtensa: Use clrsb helperRichard Henderson1-10/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-xtensa: Use clz opcodeRichard Henderson3-17/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth21-0/+8786
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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