| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-01-16 | target-xtensa: implement RER/WER instructions | Max Filippov | 6 | -3/+44 |
| 2017-01-15 | target/xtensa: implement MEMCTL SR | Max Filippov | 6 | -0/+68 |
| 2017-01-15 | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov | 1 | -2/+2 |
| 2017-01-15 | target/xtensa: don't continue translation after exception | Max Filippov | 1 | -1/+4 |
| 2017-01-15 | target/xtensa: support icount | Max Filippov | 3 | -45/+143 |
| 2017-01-15 | target/xtensa: refactor CCOUNT/CCOMPARE | Max Filippov | 4 | -46/+51 |
| 2017-01-15 | target/xtensa: implement RUNSTALL | Max Filippov | 3 | -2/+17 |
| 2017-01-15 | target/xtensa: add static vectors selection | Max Filippov | 3 | -3/+20 |
| 2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 1 | -1/+1 |
| 2017-01-10 | target-xtensa: Use clrsb helper | Richard Henderson | 1 | -10/+1 |
| 2017-01-10 | target-xtensa: Use clz opcode | Richard Henderson | 3 | -17/+11 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 21 | -0/+8786 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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