Age | Commit message (Expand) | Author | Files | Lines |
2021-09-14 | accel/tcg: Add DisasContextBase argument to translator_ld* | Ilya Leoshkevich | 1 | -2/+3 |
2021-07-21 | accel/tcg: Remove TranslatorOps.breakpoint_check | Richard Henderson | 1 | -17/+0 |
2021-07-09 | target/xtensa: Use translator_use_goto_tb | Richard Henderson | 1 | -5/+1 |
2021-07-09 | tcg: Avoid including 'trace-tcg.h' in target translate.c | Philippe Mathieu-Daudé | 1 | -1/+0 |
2021-05-20 | target/xtensa: clean up unaligned access | Max Filippov | 1 | -59/+61 |
2021-05-20 | target/xtensa: fix access ring in l32ex | Max Filippov | 1 | -1/+1 |
2021-05-20 | target/xtensa: don't generate extra EXCP_DEBUG on exception | Max Filippov | 1 | -6/+0 |
2021-05-20 | target/xtensa: Make sure that tb->size != 0 | Ilya Leoshkevich | 1 | -0/+3 |
2021-03-10 | semihosting: Move include/hw/semihosting/ -> include/semihosting/ | Philippe Mathieu-Daudé | 1 | -1/+1 |
2020-08-21 | target/xtensa: implement FPU division and square root | Max Filippov | 1 | -0/+104 |
2020-08-21 | target/xtensa: add DFPU registers and opcodes | Max Filippov | 1 | -23/+1103 |
2020-08-21 | target/xtensa: don't access BR regfile directly | Max Filippov | 1 | -4/+16 |
2020-08-21 | target/xtensa: move FSR/FCR register accessors | Max Filippov | 1 | -32/+32 |
2020-08-21 | target/xtensa: rename FPU2000 translators and helpers | Max Filippov | 1 | -35/+35 |
2020-08-21 | target/xtensa: support copying registers up to 64 bits wide | Max Filippov | 1 | -5/+21 |
2020-08-21 | target/xtensa: add geometry to xtensa_get_regfile_by_name | Max Filippov | 1 | -8/+27 |
2020-08-21 | target/xtensa: make opcode properties more dynamic | Max Filippov | 1 | -261/+277 |
2020-06-22 | target/xtensa: drop gen_io_end call | Max Filippov | 1 | -3/+0 |
2020-05-17 | target/xtensa: fix simcall for newer hardware | Max Filippov | 1 | -3/+6 |
2020-04-30 | target/xtensa: work around missing SR definitions | Max Filippov | 1 | -14/+34 |
2020-04-07 | target/xtensa: statically allocate xtensa_insnbufs in DisasContext | Max Filippov | 1 | -16/+2 |
2020-04-07 | target/xtensa: fix pasto in pfwait.r opcode name | Max Filippov | 1 | -1/+1 |
2020-04-07 | target/xtensa: add FIXME for translation memory leak | Alex Bennée | 1 | -0/+5 |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 1 | -1/+1 |
2020-01-06 | target/xtensa: fix ps.ring use in MPU configs | Max Filippov | 1 | -1/+2 |
2019-10-28 | target/xtensa: fetch code with translator_ld | Emilio G. Cota | 1 | -2/+2 |
2019-08-20 | icount: remove unnecessary gen_io_end calls | Pavel Dovgalyuk | 1 | -15/+0 |
2019-08-16 | Clean up inclusion of sysemu/sysemu.h | Markus Armbruster | 1 | -1/+0 |
2019-05-28 | semihosting: move semihosting configuration into its own directory | Alex Bennée | 1 | -1/+1 |
2019-05-21 | Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging | Peter Maydell | 1 | -1005/+1942 |
2019-05-15 | target/xtensa: implement exclusive access option | Max Filippov | 1 | -0/+100 |
2019-05-15 | target/xtensa: implement block prefetch option opcodes | Max Filippov | 1 | -0/+42 |
2019-05-14 | target/xtensa: implement DIWBUI.P opcode | Max Filippov | 1 | -0/+10 |
2019-05-13 | target/xtensa: Use tcg_gen_abs_i32 | Richard Henderson | 1 | -8/+1 |
2019-05-10 | target/xtensa: implement MPU option | Max Filippov | 1 | -0/+146 |
2019-05-10 | target/xtensa: add parity/ECC option SRs | Max Filippov | 1 | -0/+162 |
2019-05-10 | target/xtensa: get rid of centralized SR properties | Max Filippov | 1 | -1005/+1482 |
2019-04-24 | tcg: Hoist max_insns computation to tb_gen_code | Richard Henderson | 1 | -2/+2 |
2019-04-18 | qom/cpu: Simplify how CPUClass:cpu_dump_state() prints | Markus Armbruster | 1 | -19/+21 |
2019-03-21 | target/xtensa: fix break_dependency for repeated resources | Max Filippov | 1 | -1/+0 |
2019-02-28 | target/xtensa: implement PREFCTL SR | Max Filippov | 1 | -0/+16 |
2019-02-28 | target/xtensa: prioritize load/store in FLIX bundles | Max Filippov | 1 | -5/+32 |
2019-02-28 | target/xtensa: break circular register dependencies | Max Filippov | 1 | -4/+123 |
2019-02-28 | target/xtensa: reorganize access to boolean registers | Max Filippov | 1 | -8/+42 |
2019-02-28 | target/xtensa: reorganize access to MAC16 registers | Max Filippov | 1 | -94/+92 |
2019-02-28 | target/xtensa: reorganize register handling in translators | Max Filippov | 1 | -341/+359 |
2019-02-28 | target/xtensa: only rotate window in the retw helper | Max Filippov | 1 | -2/+7 |
2019-02-28 | target/xtensa: move WINDOW_BASE SR update to postprocessing | Max Filippov | 1 | -8/+22 |
2019-02-28 | target/xtensa: add generic instruction post-processing | Max Filippov | 1 | -8/+25 |
2019-02-28 | target/xtensa: sort FLIX instruction opcodes | Max Filippov | 1 | -8/+219 |