riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-28	semihosting: move semihosting configuration into its own directory	Alex Bennée	1	-1/+1
2019-05-21	Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging	Peter Maydell	1	-1005/+1942
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov	1	-0/+100
2019-05-15	target/xtensa: implement block prefetch option opcodes	Max Filippov	1	-0/+42
2019-05-14	target/xtensa: implement DIWBUI.P opcode	Max Filippov	1	-0/+10
2019-05-13	target/xtensa: Use tcg_gen_abs_i32	Richard Henderson	1	-8/+1
2019-05-10	target/xtensa: implement MPU option	Max Filippov	1	-0/+146
2019-05-10	target/xtensa: add parity/ECC option SRs	Max Filippov	1	-0/+162
2019-05-10	target/xtensa: get rid of centralized SR properties	Max Filippov	1	-1005/+1482
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	1	-2/+2
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-19/+21
2019-03-21	target/xtensa: fix break_dependency for repeated resources	Max Filippov	1	-1/+0
2019-02-28	target/xtensa: implement PREFCTL SR	Max Filippov	1	-0/+16
2019-02-28	target/xtensa: prioritize load/store in FLIX bundles	Max Filippov	1	-5/+32
2019-02-28	target/xtensa: break circular register dependencies	Max Filippov	1	-4/+123
2019-02-28	target/xtensa: reorganize access to boolean registers	Max Filippov	1	-8/+42
2019-02-28	target/xtensa: reorganize access to MAC16 registers	Max Filippov	1	-94/+92
2019-02-28	target/xtensa: reorganize register handling in translators	Max Filippov	1	-341/+359
2019-02-28	target/xtensa: only rotate window in the retw helper	Max Filippov	1	-2/+7
2019-02-28	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	1	-8/+22
2019-02-28	target/xtensa: add generic instruction post-processing	Max Filippov	1	-8/+25
2019-02-28	target/xtensa: sort FLIX instruction opcodes	Max Filippov	1	-8/+219
2019-02-18	target/xtensa: implement wide branches and loops	Max Filippov	1	-27/+102
2019-02-18	target/xtensa: allow multiple names for single opcode	Max Filippov	1	-56/+44
2019-02-18	target/xtensa: don't require opcode table sorting	Max Filippov	1	-14/+0
2019-02-11	target/xtensa: get rid of gen_callw[i]	Max Filippov	1	-21/+14
2019-02-10	target/xtensa: don't specify windowed registers manually	Max Filippov	1	-483/+10
2019-01-24	target/xtensa: fix access to the INTERRUPT SR	Max Filippov	1	-12/+2
2019-01-11	target/xtensa: rework zero overhead loops implementation	Max Filippov	1	-37/+16
2018-10-01	target/xtensa: extract gen_check_interrupts call	Max Filippov	1	-25/+53
2018-10-01	target/xtensa: make rsr/wsr helpers return void	Max Filippov	1	-66/+36
2018-10-01	target/xtensa: extract unconditional TB termination via slot 0	Max Filippov	1	-47/+36
2018-10-01	target/xtensa: always end TB on CCOUNT access/CCOMPARE write	Max Filippov	1	-8/+5
2018-10-01	target/xtensa: change SR number checks to assertions	Max Filippov	1	-36/+29
2018-10-01	target/xtensa: extract unconditional TB termination	Max Filippov	1	-39/+28
2018-10-01	target/xtensa: extract test for division by zero	Max Filippov	1	-22/+31
2018-10-01	target/xtensa: extract test for cpdisabled exception	Max Filippov	1	-108/+122
2018-10-01	target/xtensa: extract test for alloca exception	Max Filippov	1	-3/+8
2018-10-01	target/xtensa: extract test for window underflow exception	Max Filippov	1	-0/+9
2018-10-01	target/xtensa: extract test for window overflow exception	Max Filippov	1	-582/+880
2018-10-01	target/xtensa: extract test for debug exception	Max Filippov	1	-10/+13
2018-10-01	target/xtensa: extract test for syscall instruction	Max Filippov	1	-7/+6
2018-10-01	target/xtensa: extract test for privileged instruction	Max Filippov	1	-93/+294
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	1	-35/+332
2018-09-17	target/xtensa: fix s32c1i TCGMemOp flags	Max Filippov	1	-1/+1
2018-09-17	target/xtensa: fix FPU2000 bugs	Max Filippov	1	-3/+3
2018-06-30	target/xtensa: Convert to TranslatorOps	Richard Henderson	1	-101/+116
2018-06-30	target/xtensa: Change gen_intermediate_code dc to pointer	Richard Henderson	1	-61/+61
2018-06-30	target/xtensa: Convert to DisasContextBase	Richard Henderson	1	-47/+44
2018-06-30	target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN	Richard Henderson	1	-12/+9