| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-01-11 | target/xtensa: rework zero overhead loops implementation | Max Filippov | 1 | -0/+1 |
| 2018-06-30 | target/xtensa: check zero overhead loop alignment | Max Filippov | 1 | -0/+1 |
| 2018-03-13 | target/xtensa: use correct number of registers in gdbstub | Max Filippov | 1 | -3/+8 |
| 2018-01-11 | target/xtensa: fix default sysrom/sysram addresses | Max Filippov | 1 | -4/+4 |
| 2017-02-23 | target/xtensa: sim: instantiate local memories | Max Filippov | 1 | -0/+160 |
| 2017-01-16 | target-xtensa: implement RER/WER instructions | Max Filippov | 1 | -1/+6 |
| 2017-01-15 | target/xtensa: implement MEMCTL SR | Max Filippov | 1 | -0/+15 |
| 2017-01-15 | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov | 1 | -2/+2 |
| 2017-01-15 | target/xtensa: add static vectors selection | Max Filippov | 1 | -1/+10 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+602 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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