riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-09-17	target/xtensa: convert to do_transaction_failed	Max Filippov	1	-1/+1
2018-08-06	target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn	Thomas Huth	1	-1/+1
2018-06-01	target: Do not include "exec/exec-all.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-03-16	target/xtensa: add linux-user support	Max Filippov	1	-4/+22
2018-02-05	qdev: use device_class_set_parent_realize/unrealize/reset()	Philippe Mathieu-Daudé	1	-2/+2
2018-01-09	target/xtensa: implement disassembler	Max Filippov	1	-0/+9
2017-10-27	xtensa: cleanup cpu type name composition	Igor Mammedov	1	-1/+1
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-6/+1
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-4/+0
2017-09-01	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	1	-0/+3
2017-01-16	target-xtensa: implement RER/WER instructions	Max Filippov	1	-0/+6
2017-01-15	target/xtensa: implement MEMCTL SR	Max Filippov	1	-0/+1
2017-01-15	target/xtensa: implement RUNSTALL	Max Filippov	1	-1/+2
2017-01-15	target/xtensa: add static vectors selection	Max Filippov	1	-1/+1
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+184