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2024-02-03target/sparc: Use TCG_COND_TSTEQ in gen_op_mulsccRichard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASKRichard Henderson1-7/+0
These macros are no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org>
2024-02-03target/sparc: Split fcc out of env->fsrRichard Henderson4-522/+198
Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove cpu_fsrRichard Henderson3-113/+114
Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
2024-02-03target/sparc: Split cexc and ftt from env->fsrRichard Henderson4-38/+48
These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
2024-02-03target/sparc: Merge check_ieee_exceptions with FPop helpersRichard Henderson3-129/+219
If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>
2024-02-03target/sparc: Clear cexc and ftt in do_check_ieee_exceptionsRichard Henderson2-16/+2
Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org>
2024-02-03target/sparc: Split ver from env->fsrRichard Henderson3-16/+23
This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>
2024-02-03target/sparc: Introduce cpu_get_fsr, cpu_put_fsrRichard Henderson7-12/+70
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove qt0, qt1 temporariesRichard Henderson3-8/+0
These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FdmulqRichard Henderson3-16/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FdTOq, FxTOqRichard Henderson3-10/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FsTOq, FiTOqRichard Henderson3-10/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FCMPq, FCMPEqRichard Henderson3-52/+41
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FqTOd, FqTOxRichard Henderson3-9/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FqTOs, FqTOiRichard Henderson3-9/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVqRichard Henderson3-28/+26
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FSQRTqRichard Henderson3-8/+32
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
2024-02-03target/sparc: Inline FNEG, FABSRichard Henderson3-72/+30
These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
2024-02-03target/sparc: Introduce gen_{load,store}_fpr_QRichard Henderson1-6/+19
Use them for trans_FMOVq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove gen_dest_fpr_FRichard Henderson1-11/+6
Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org>
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILLRichard Henderson1-16/+15
Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org>
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPYRichard Henderson1-19/+26
Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org>
2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson3-3/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson2-7/+1
For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/sparc: Populate CPUClass.mmu_indexRichard Henderson2-28/+35
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-1/+1
QEMU coding style recommends using structure typedefs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson1-1/+1
Makes gen_intermediate_code() signature target agnostic so the function can be called from accel/tcg/translate-all.c without target specifics. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-9-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-08system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi3-14/+14
The Big QEMU Lock (BQL) has many names and they are confusing. The actual QemuMutex variable is called qemu_global_mutex but it's commonly referred to as the BQL in discussions and some code comments. The locking APIs, however, are called qemu_mutex_lock_iothread() and qemu_mutex_unlock_iothread(). The "iothread" name is historic and comes from when the main thread was split into into KVM vcpu threads and the "iothread" (now called the main loop thread). I have contributed to the confusion myself by introducing a separate --object iothread, a separate concept unrelated to the BQL. The "iothread" name is no longer appropriate for the BQL. Rename the locking APIs to: - void bql_lock(void) - void bql_unlock(void) - bool bql_locked(void) There are more APIs with "iothread" in their names. Subsequent patches will rename them. There are also comments and documentation that will be updated in later patches. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Acked-by: Fabiano Rosas <farosas@suse.de> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Peter Xu <peterx@redhat.com> Acked-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Acked-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20240102153529.486531-2-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-01-05target/sparc: Simplify qemu_irq_ackClément Chigot2-2/+2
This is a simple cleanup, since env is passed to qemu_irq_ack it can be accessed from inside qemu_irq_ack. Just drop this parameter. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240105102421.163554-7-chigot@adacore.com>
2023-12-29target/sparc: Constify VMState in machine.cRichard Henderson1-4/+4
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-18-richard.henderson@linaro.org>
2023-11-14target/sparc: Fix RETURNRichard Henderson1-1/+1
Perform window restore before pc update. Required in order to recognize any window underflow trap with the current pc. Fixes: 86b82fe021f4 ("target/sparc: Move JMPL, RETT, RETURN to decodetree") Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2-20/+16
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-13-philmd@linaro.org>
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2-3/+4
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-7-philmd@linaro.org>
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé2-4/+0
Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-11-05target/sparc: Check for invalid cond in gen_compare_regRichard Henderson1-19/+26
Consolidate the test here; drop the "inverted logic". Fix MOVr and FMOVR, which were missing the invalid test. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIV inlineRichard Henderson2-14/+56
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIVX and SDIVX inlineRichard Henderson4-44/+97
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Discard cpu_cond at the end of each insnRichard Henderson1-0/+27
If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Record entire jump condition in DisasContextRichard Henderson1-11/+16
Use the original condition instead of consuming cpu_cond, which will now only be live along exception paths. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge gen_op_next_insn into only callerRichard Henderson1-7/+2
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Pass displacement to advance_jump_condRichard Henderson1-7/+5
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_condRichard Henderson1-44/+30
Handle these via TCG_COND_{ALWAYS,NEVER}. Allow dc->npc to be variable, using gen_mov_pc_npc. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge gen_branch2 into advance_pcRichard Henderson1-14/+14
The function had only one caller. Canonicalize the cpu_cond test to TCG_COND_NE, the "natural" sense of its value. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Do flush_cond in advance_jump_condRichard Henderson1-6/+4
Do this here instead of in each caller. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Always copy conditions into a new temporaryRichard Henderson1-1/+2
This will allow the condition to live across changes to the global cc variables. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Change DisasCompare.c2 to intRichard Henderson1-15/+18
We don't require c2 to be variable, so emphasize that. We don't currently require c2 to be non-zero, but that will change. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove DisasCompare.is_boolRichard Henderson1-15/+7
Since we're going to feed cpu_cond to another comparison, we don't reqire a boolean value -- anything non-zero is sufficient. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP leftoversRichard Henderson9-173/+26
All instructions have been converted to generate full condition codes explicitly. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTVRichard Henderson4-200/+32
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>