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2023-10-25target/sparc: Use tcg_gen_vec_{add,sub}*Richard Henderson3-79/+7
Replace the local helpers for the same integer operations. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetreeRichard Henderson2-42/+56
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetreeRichard Henderson2-43/+62
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move BMASK to decodetreeRichard Henderson2-9/+15
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move ADDRALIGN* to decodetreeRichard Henderson2-25/+34
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move ARRAY* to decodetreeRichard Henderson2-21/+40
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move EDGE* to decodetreeRichard Henderson2-160/+133
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Merge LDFSR, LDXFSR implementationsRichard Henderson3-46/+16
Combine the helper to a single set_fsr(). Perform the mask and merge inline. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move LDFSR, STFSR to decodetreeRichard Henderson2-92/+64
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move asi fp load/store to decodetreeRichard Henderson2-143/+81
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move simple fp load/store to decodetreeRichard Henderson2-100/+113
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Split out fp ldst functions with asi precomputedRichard Henderson1-58/+80
Take the operation size from the MemOp instead of a separate parameter. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move PREFETCH, PREFETCHA to decodetreeRichard Henderson2-17/+14
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move CASA, CASXA to decodetreeRichard Henderson2-43/+36
Remove gen_cas_asi, gen_casx_asi. Rename gen_cas_asi0 to gen_cas_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move SWAP, SWAPA to decodetreeRichard Henderson2-33/+29
Remove gen_swap_asi. Rename gen_swap_asi0 to gen_swap_asi. Merge gen_swap into gen_swap_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move LDSTUB, LDSTUBA to decodetreeRichard Henderson2-24/+26
Remove gen_ldstub_asi. Rename gen_ldstub_asi0 to gen_ldstub_asi. Merge gen_ldstub into gen_ldstub_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move asi integer load/store to decodetreeRichard Henderson2-111/+48
Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move simple integer load/store to decodetreeRichard Henderson2-76/+142
Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINXRichard Henderson1-8/+40
Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Split out ldst functions with asi pre-computedRichard Henderson1-85/+116
As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Drop ifdef around get_asi and friendsRichard Henderson1-117/+72
Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Split out resolve_asiRichard Henderson1-4/+21
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move DONE, RETRY to decodetreeRichard Henderson2-62/+29
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move FLUSH, SAVE, RESTORE to decodetreeRichard Henderson2-10/+29
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move JMPL, RETT, RETURN to decodetreeRichard Henderson2-45/+88
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Convert remaining v8 coproc insns to decodetreeRichard Henderson2-26/+17
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move POPC to decodetreeRichard Henderson2-47/+12
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move MOVcc, MOVR to decodetreeRichard Henderson2-56/+64
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move SLL, SRL, SRA to decodetreeRichard Henderson2-104/+92
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move TADD, TSUB, MULS to decodetreeRichard Henderson3-30/+29
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move UDIV, SDIV to decodetreeRichard Henderson3-33/+27
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move UDIVX, SDIVX to decodetreeRichard Henderson2-9/+18
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move SUBC to decodetreeRichard Henderson2-50/+90
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move UMUL, SMUL to decodetreeRichard Henderson2-18/+6
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move MULX to decodetreeRichard Henderson2-5/+6
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move ADDC to decodetreeRichard Henderson2-55/+94
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move basic arithmetic to decodetreeRichard Henderson2-103/+94
Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_verRichard Henderson1-19/+13
Use direct loads and stores to env instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmprRichard Henderson1-27/+14
Use direct loads and stores to env instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Remove cpu_wimRichard Henderson1-6/+8
Use direct loads and stores to env instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move WRTBR, WRHPR to decodetreeRichard Henderson2-54/+66
Implement htstate in the obvious way. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move WRWIM, WRPR to decodetreeRichard Henderson2-136/+200
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move WRPSR, SAVED, RESTORED to decodetreeRichard Henderson2-33/+39
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move WRASR to decodetreeRichard Henderson2-156/+216
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move RDTBR, FLUSHW to decodetreeRichard Henderson2-12/+16
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move RDWIM, RDPR to decodetreeRichard Henderson2-138/+204
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move RDPSR, RDHPR to decodetreeRichard Henderson2-43/+83
Implement htstate in the obvious way. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/847 Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move RDASR, STBAR, MEMBAR to decodetreeRichard Henderson2-129/+235
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move Tcc to decodetreeRichard Henderson2-79/+89
Use the new delay_exceptionv function in the implementation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Move SETHI to decodetreeRichard Henderson2-35/+21
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-02-01 21:49:00 +0000