aboutsummaryrefslogtreecommitdiff
path: root/target/sparc
AgeCommit message (Expand)AuthorFilesLines
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-1/+4
2017-10-27sparc: cleanup cpu type name compositionIgor Mammedov2-1/+4
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/sparc: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson3-13/+3
2017-10-24tcg: Remove GET_TCGV_* and MAKE_TCGV_*Richard Henderson1-10/+5
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
2017-09-27migration: pre_save return intDr. David Alan Gilbert1-1/+3
2017-09-14sparc: Fix typedef clashDr. David Alan Gilbert1-2/+2
2017-09-01sparc: replace cpu_sparc_init() with cpu_generic_init()Igor Mammedov2-7/+1
2017-09-01sparc: make cpu feature parsing property basedIgor Mammedov1-133/+82
2017-09-01sparc: move adhoc CPUSPARCState initialization to realize timeIgor Mammedov1-15/+15
2017-09-01sparc: convert cpu features to qdev propertiesIgor Mammedov1-0/+66
2017-09-01sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov8-40/+33
2017-09-01sparc: convert cpu models to SPARC cpu subclassesIgor Mammedov2-39/+83
2017-08-01trace-events: fix code style: print 0x before hex numbersVladimir Sementsov-Ogievskiy1-15/+15
2017-07-31docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé1-1/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-19target/sparc: optimize gen_op_mulscc() using deposit opPhilippe Mathieu-Daudé1-4/+1
2017-07-19target/sparc: optimize various functions using extract opPhilippe Mathieu-Daudé1-10/+5
2017-05-23shutdown: Add source information to SHUTDOWN and RESETEric Blake1-1/+1
2017-03-09sparc/sparc64: grab BQL before calling cpu_check_irqsAlex Bennée2-0/+16
2017-03-02target/sparc: Restore ldstub of odd asisRichard Henderson1-2/+25
2017-02-24cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée1-3/+5
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth1-0/+4
2017-01-24migration: extend VMStateInfoJianjun Duan1-2/+4
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko1-0/+11
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2-8/+47
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko1-0/+31
2017-01-18target-sparc: add more registers to dump_mmuArtyom Tarasenko1-0/+2
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko1-0/+22
2017-01-18target-sparc: allow 256M sized pagesArtyom Tarasenko1-17/+1
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko1-36/+15
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2-22/+104
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko3-36/+24
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko1-2/+4
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko1-0/+1
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko1-14/+18
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2-5/+4
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko1-1/+1
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko1-2/+5
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko6-7/+58
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko3-5/+39
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2-3/+7
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko1-0/+11
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko3-0/+26
generated by cgit v1.1 at 2024-12-27 12:35:38 +0000