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path: root/target/sparc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2019-10-28target/sparc: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-7/+7
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk1-16/+0
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2018-06-17SPARC64: add icount supportMark Cave-Ayland1-1/+110
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-8/+8
2018-05-09target/sparc: convert to TranslatorOpsEmilio G. Cota1-88/+86
2018-05-09target/sparc: convert to DisasContextBaseEmilio G. Cota1-47/+45
2018-05-09target/sparc: convert to DisasJumpTypeEmilio G. Cota1-12/+15
2018-03-08sparc: fix leon3 casa instruction when MMU is disabledKONRAD Frederic1-0/+5
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-1/+1
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/sparc: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-8/+1
2017-10-24tcg: Remove GET_TCGV_* and MAKE_TCGV_*Richard Henderson1-10/+5
2017-09-01sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov1-1/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-19target/sparc: optimize gen_op_mulscc() using deposit opPhilippe Mathieu-Daudé1-4/+1
2017-07-19target/sparc: optimize various functions using extract opPhilippe Mathieu-Daudé1-10/+5
2017-03-02target/sparc: Restore ldstub of odd asisRichard Henderson1-2/+25
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko1-0/+11
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko1-1/+1
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko1-1/+1
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko1-2/+5
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko1-2/+1
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko1-1/+5
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko1-0/+11
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko1-5/+19
2017-01-10target-sparc: Use ctpop helperRichard Henderson1-1/+1
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+5924
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