Age | Commit message (Expand) | Author | Files | Lines |
2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier | 1 | -3/+3 |
2017-09-01 | sparc: embed sparc_def_t into CPUSPARCState | Igor Mammedov | 1 | -7/+7 |
2017-02-24 | cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap | Alex Bennée | 1 | -3/+5 |
2017-01-18 | target-sparc: store the UA2005 entries in sun4u format | Artyom Tarasenko | 1 | -8/+44 |
2017-01-18 | target-sparc: implement UA2005 ASI_MMU (0x21) | Artyom Tarasenko | 1 | -0/+31 |
2017-01-18 | target-sparc: implement auto-demapping for UA2005 CPUs | Artyom Tarasenko | 1 | -0/+22 |
2017-01-18 | target-sparc: simplify ultrasparc_tsb_pointer | Artyom Tarasenko | 1 | -36/+15 |
2017-01-18 | target-sparc: implement UA2005 TSB Pointers | Artyom Tarasenko | 1 | -22/+102 |
2017-01-18 | target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs | Artyom Tarasenko | 1 | -4/+4 |
2017-01-18 | target-sparc: replace the last tlb entry when no free entries left | Artyom Tarasenko | 1 | -2/+4 |
2017-01-18 | target-sparc: ignore writes to UA2005 CPU mondo queue register | Artyom Tarasenko | 1 | -0/+1 |
2017-01-18 | target-sparc: allow priveleged ASIs in hyperprivileged mode | Artyom Tarasenko | 1 | -14/+18 |
2017-01-18 | target-sparc: implement UA2005 scratchpad registers | Artyom Tarasenko | 1 | -0/+24 |
2017-01-18 | target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE | Artyom Tarasenko | 1 | -3/+2 |
2017-01-18 | target-sparc: use explicit mmu register pointers | Artyom Tarasenko | 1 | -12/+54 |
2017-01-18 | target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode | Artyom Tarasenko | 1 | -2/+13 |
2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 1 | -6/+6 |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+1709 |