| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-05-10 | target/sparc: Convert to CPUClass::tlb_fill | Richard Henderson | 1 | -2/+3 |
| 2019-04-18 | qom/cpu: Simplify how CPUClass:cpu_dump_state() prints | Markus Armbruster | 1 | -2/+1 |
| 2019-04-18 | target: Clean up how the dump_mmu() print | Markus Armbruster | 1 | -1/+1 |
| 2019-04-18 | target: Simplify how the TARGET_cpu_list() print | Markus Armbruster | 1 | -1/+1 |
| 2018-03-19 | cpu: get rid of unused cpu_init() defines | Igor Mammedov | 1 | -4/+0 |
| 2018-03-19 | cpu: add CPU_RESOLVING_TYPE macro | Igor Mammedov | 1 | -0/+1 |
| 2018-02-21 | target/*/cpu.h: remove softfloat.h | Alex Bennée | 1 | -2/+0 |
| 2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier | 1 | -1/+1 |
| 2017-10-27 | sparc: cleanup cpu type name composition | Igor Mammedov | 1 | -0/+3 |
| 2017-10-24 | qom: Introduce CPUClass.tcg_initialize | Richard Henderson | 1 | -1/+1 |
| 2017-09-14 | sparc: Fix typedef clash | Dr. David Alan Gilbert | 1 | -2/+2 |
| 2017-09-01 | sparc: replace cpu_sparc_init() with cpu_generic_init() | Igor Mammedov | 1 | -2/+1 |
| 2017-09-01 | sparc: embed sparc_def_t into CPUSPARCState | Igor Mammedov | 1 | -4/+4 |
| 2017-01-18 | target-sparc: store the UA2005 entries in sun4u format | Artyom Tarasenko | 1 | -0/+3 |
| 2017-01-18 | target-sparc: implement UA2005 TSB Pointers | Artyom Tarasenko | 1 | -0/+2 |
| 2017-01-18 | target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs | Artyom Tarasenko | 1 | -30/+18 |
| 2017-01-18 | target-sparc: use direct address translation in hyperprivileged mode | Artyom Tarasenko | 1 | -4/+3 |
| 2017-01-18 | target-sparc: implement UA2005 GL register | Artyom Tarasenko | 1 | -0/+2 |
| 2017-01-18 | target-sparc: implement UA2005 hypervisor traps | Artyom Tarasenko | 1 | -0/+1 |
| 2017-01-18 | target-sparc: hypervisor mode takes over nucleus mode | Artyom Tarasenko | 1 | -2/+2 |
| 2017-01-18 | target-sparc: implement UA2005 scratchpad registers | Artyom Tarasenko | 1 | -0/+1 |
| 2017-01-18 | target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode | Artyom Tarasenko | 1 | -1/+2 |
| 2017-01-18 | target-sparc: add UltraSPARC T1 TLB #defines | Artyom Tarasenko | 1 | -0/+4 |
| 2017-01-18 | target-sparc: add UA2005 TTE bit #defines | Artyom Tarasenko | 1 | -0/+17 |
| 2017-01-18 | target-sparc: use explicit mmu register pointers | Artyom Tarasenko | 1 | -0/+4 |
| 2017-01-18 | target-sparc: store cpu super- and hypervisor flags in TB | Artyom Tarasenko | 1 | -0/+17 |
| 2017-01-18 | target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode | Artyom Tarasenko | 1 | -0/+2 |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée | 1 | -0/+3 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+779 |
