index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
sparc
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2018-03-19
cpu: get rid of unused cpu_init() defines
Igor Mammedov
1
-4
/
+0
2018-03-19
cpu: add CPU_RESOLVING_TYPE macro
Igor Mammedov
1
-0
/
+1
2018-02-21
target/*/cpu.h: remove softfloat.h
Alex Bennée
1
-2
/
+0
2018-01-25
accel/tcg: add size paremeter in tlb_fill()
Laurent Vivier
1
-1
/
+1
2017-10-27
sparc: cleanup cpu type name composition
Igor Mammedov
1
-0
/
+3
2017-10-24
qom: Introduce CPUClass.tcg_initialize
Richard Henderson
1
-1
/
+1
2017-09-14
sparc: Fix typedef clash
Dr. David Alan Gilbert
1
-2
/
+2
2017-09-01
sparc: replace cpu_sparc_init() with cpu_generic_init()
Igor Mammedov
1
-2
/
+1
2017-09-01
sparc: embed sparc_def_t into CPUSPARCState
Igor Mammedov
1
-4
/
+4
2017-01-18
target-sparc: store the UA2005 entries in sun4u format
Artyom Tarasenko
1
-0
/
+3
2017-01-18
target-sparc: implement UA2005 TSB Pointers
Artyom Tarasenko
1
-0
/
+2
2017-01-18
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
Artyom Tarasenko
1
-30
/
+18
2017-01-18
target-sparc: use direct address translation in hyperprivileged mode
Artyom Tarasenko
1
-4
/
+3
2017-01-18
target-sparc: implement UA2005 GL register
Artyom Tarasenko
1
-0
/
+2
2017-01-18
target-sparc: implement UA2005 hypervisor traps
Artyom Tarasenko
1
-0
/
+1
2017-01-18
target-sparc: hypervisor mode takes over nucleus mode
Artyom Tarasenko
1
-2
/
+2
2017-01-18
target-sparc: implement UA2005 scratchpad registers
Artyom Tarasenko
1
-0
/
+1
2017-01-18
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode
Artyom Tarasenko
1
-1
/
+2
2017-01-18
target-sparc: add UltraSPARC T1 TLB #defines
Artyom Tarasenko
1
-0
/
+4
2017-01-18
target-sparc: add UA2005 TTE bit #defines
Artyom Tarasenko
1
-0
/
+17
2017-01-18
target-sparc: use explicit mmu register pointers
Artyom Tarasenko
1
-0
/
+4
2017-01-18
target-sparc: store cpu super- and hypervisor flags in TB
Artyom Tarasenko
1
-0
/
+17
2017-01-18
target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode
Artyom Tarasenko
1
-0
/
+2
2017-01-13
qom/cpu: move tlb_flush to cpu_common_reset
Alex Bennée
1
-0
/
+3
2016-12-20
Move target-* CPU file into a target/ folder
Thomas Huth
1
-0
/
+779