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path: root/target/sparc/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-5/+5
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-0/+1
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé1-2/+0
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-3/+2
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-16target/sparc: Make sparc_cpu_dump_state() staticPhilippe Mathieu-Daudé1-1/+0
2021-05-04hw/sparc: Allow building without the leon3 machinePhilippe Mathieu-Daudé1-6/+0
2020-12-18linux-user/sparc: Handle tstate in sparc64_get/set_context()Peter Maydell1-4/+20
2020-12-18linux-user/sparc: Correct sparc64_get/set_context() FPU handlingPeter Maydell1-1/+3
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-1/+1
2019-11-06target/sparc: Define an enumeration for accessing env->regwptrRichard Henderson1-0/+33
2019-09-17target/sparc: Switch to do_transaction_failed() hookPeter Maydell1-3/+5
2019-09-03target/sparc: sun4u Invert Endian TTE bitTony Nguyen1-0/+2
2019-08-20configure: Define target access alignment in configuretony.nguyen@bt.com1-2/+0
2019-08-16migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster1-1/+1
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
2019-06-10target/sparc: Use env_cpu, env_archcpuRichard Henderson1-5/+0
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson1-18/+2
2019-05-10target/sparc: Convert to CPUClass::tlb_fillRichard Henderson1-2/+3
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-2/+1
2019-04-18target: Clean up how the dump_mmu() printMarkus Armbruster1-1/+1
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster1-1/+1
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-4/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée1-2/+0
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-1/+1
2017-10-27sparc: cleanup cpu type name compositionIgor Mammedov1-0/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-1/+1
2017-09-14sparc: Fix typedef clashDr. David Alan Gilbert1-2/+2
2017-09-01sparc: replace cpu_sparc_init() with cpu_generic_init()Igor Mammedov1-2/+1
2017-09-01sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov1-4/+4
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko1-0/+3
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko1-0/+2
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko1-30/+18
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko1-4/+3
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko1-0/+2
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko1-0/+1
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko1-2/+2
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko1-0/+1
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko1-1/+2
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko1-0/+4
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko1-0/+17
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko1-0/+4
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