aboutsummaryrefslogtreecommitdiff
path: root/target/sh4
AgeCommit message (Expand)AuthorFilesLines
2020-04-15gdbstub: Introduce gdb_get_float32() to get 32-bit float registersPhilippe Mathieu-Daudé1-4/+2
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-5/+5
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2-5/+5
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée2-2/+2
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz1-2/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2020-01-15target/sh4: Remove MMU_MODE{0,1}_SUFFIXRichard Henderson1-2/+0
2019-10-28target/sh4: fetch code with translator_ldEmilio G. Cota1-2/+2
2019-08-22Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...Peter Maydell1-1/+1
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
2019-08-20configure: Define target access alignment in configuretony.nguyen@bt.com1-2/+0
2019-08-19targets (various): use softfloat-helpers.h where we canAlex Bennée1-2/+1
2019-08-16sysemu: Split sysemu/runstate.h off sysemu/sysemu.hMarkus Armbruster1-1/+2
2019-07-02hmp: Move hmp.h to include/monitor/Markus Armbruster1-1/+1
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster3-3/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
2019-06-10target/sh4: Use env_cpu, env_archcpuRichard Henderson3-25/+15
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2-3/+1
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson2-13/+22
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-8/+0
2019-05-10target/sh4: Convert to CPUClass::tlb_fillRichard Henderson4-118/+101
2019-05-08target/sh4: Fix LGPL information in the file headersThomas Huth5-5/+5
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2-15/+15
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2-14/+5
2018-08-20sh4: fix use_icount with linux-userLaurent Vivier1-0/+1
2018-07-09target/sh4: Fix translator.c assertion failure for gUSARichard Henderson1-37/+44
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-4/+4
2018-05-17fpu/softfloat: Specialize on snan_bit_is_oneRichard Henderson1-1/+0
2018-05-09target/sh4: convert to TranslatorOpsEmilio G. Cota1-85/+86
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-03-12qom: introduce object_class_get_list_sortedPaolo Bonzini1-14/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée3-2/+2
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-2/+2
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier3-6/+6
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-2/+2
2017-12-18target/sh4: Convert to DisasContextBaseRichard Henderson1-76/+78
2017-12-18target/sh4: Do not singlestep after exceptionsRichard Henderson1-16/+16
2017-12-18target/sh4: Convert to DisasJumpTypeRichard Henderson1-35/+30
2017-12-18target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson3-23/+64
2017-12-18target/sh4: fix TCG leak during gusa sequenceAlex Bennée1-1/+1
2017-12-18target/sh4: add missing tcg_temp_free() in _decode_opc()Philippe Mathieu-Daudé1-0/+2
2017-12-18Remove empty statementsLadi Prosek1-1/+1
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell3-72/+46
generated by cgit v1.1 at 2024-12-26 08:02:26 +0000