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path: root/target/sh4/translate.c
AgeCommit message (Expand)AuthorFilesLines
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-4/+4
2018-05-09target/sh4: convert to TranslatorOpsEmilio G. Cota1-85/+86
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-2/+2
2017-12-18target/sh4: Convert to DisasContextBaseRichard Henderson1-76/+78
2017-12-18target/sh4: Do not singlestep after exceptionsRichard Henderson1-16/+16
2017-12-18target/sh4: Convert to DisasJumpTypeRichard Henderson1-35/+30
2017-12-18target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson1-22/+60
2017-12-18target/sh4: fix TCG leak during gusa sequenceAlex Bennée1-1/+1
2017-12-18target/sh4: add missing tcg_temp_free() in _decode_opc()Philippe Mathieu-Daudé1-0/+2
2017-12-18Remove empty statementsLadi Prosek1-1/+1
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/sh4: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-7/+0
2017-10-10tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota1-2/+2
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-18target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson1-10/+20
2017-07-18target/sh4: Implement fsrraRichard Henderson1-0/+2
2017-07-18target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson1-0/+2
2017-07-18target/sh4: Implement fpchgRichard Henderson1-0/+5
2017-07-18target/sh4: Introduce CHECK_SH4ARichard Henderson1-34/+30
2017-07-18target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson1-26/+31
2017-07-18target/sh4: Tidy misc illegal insn checksRichard Henderson1-9/+13
2017-07-18target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson1-10/+14
2017-07-18target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson1-10/+4
2017-07-18target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson1-6/+5
2017-07-18target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson1-4/+4
2017-07-18target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson1-39/+36
2017-07-18target/sh4: Merge DREG into fpr64 routinesRichard Henderson1-11/+15
2017-07-18target/sh4: Eliminate unused XREG macroRichard Henderson1-1/+0
2017-07-18target/sh4: Hoist fp register bank selectionRichard Henderson1-3/+5
2017-07-18target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson1-13/+13
2017-07-18target/sh4: Unify cpu_fregs into FREGRichard Henderson1-73/+52
2017-07-18target/sh4: Hoist register bank selectionRichard Henderson1-10/+11
2017-07-18target/sh4: Recognize common gUSA sequencesRichard Henderson1-0/+321
2017-07-18target/sh4: Handle user-space atomicsRichard Henderson1-12/+126
2017-07-18target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson1-2/+2
2017-07-18target/sh4: Consolidate end-of-TB testsRichard Henderson1-14/+17
2017-07-18target/sh4: return result of fcmp using TCGAurelien Jarno1-4/+6
2017-07-18target/sh4: do not use a helper to implement fnegAurelien Jarno1-3/+2
2017-07-18target/sh4: do not check for PR bit for fabs instructionAurelien Jarno1-12/+3
2017-05-30target/sh4: fix RTE instruction delay slotAurelien Jarno1-2/+6
2017-05-30target/sh4: introduce DELAY_SLOT_MASKAurelien Jarno1-9/+8
2017-05-13target/sh4: trap unaligned accessesAurelien Jarno1-2/+4
2017-05-13target/sh4: movua.l is an SH4-A only instructionAurelien Jarno1-11/+15
2017-05-13target/sh4: implement tas.b using atomic helperAurelien Jarno1-12/+7
2017-05-13target/sh4: generate fences for SH4Aurelien Jarno1-4/+5