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2017-07-05virtio-scsi-ccw: use ioeventfd even when KVM is disabledQingFeng Hao1-1/+5
This patch is based on a similar patch from Stefan Hajnoczi - commit c324fd0a39c ("virtio-pci: use ioeventfd even when KVM is disabled") Do not check kvm_eventfds_enabled() when KVM is disabled since it always returns 0. Since commit 8c56c1a592b5092d91da8d8943c17777d6462a6f ("memory: emulate ioeventfd") it has been possible to use ioeventfds in qtest or TCG mode. This patch makes -device virtio-scsi-ccw,iothread=iothread0 work even when KVM is disabled. Currently we don't have an equivalent to "memory: emulate ioeventfd" for ccw yet, but that this doesn't hurt and qemu-iotests 068 can pass with skipping iothread arguments. I have tested that virtio-scsi-ccw works under tcg both with and without iothread. This patch fixes qemu-iotests 068, which was accidentally merged early despite the dependency on ioeventfd. Signed-off-by: QingFeng Hao <haoqf@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20170704132350.11874-2-haoqf@linux.vnet.ibm.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-05s390x: return unavailable features via query-cpu-definitionsViktor Mihajlovski1-5/+57
The response for query-cpu-definitions didn't include the unavailable-features field, which is used by libvirt to figure out whether a certain cpu model is usable on the host. The unavailable features are now computed by obtaining the host CPU model and comparing it against the known CPU models. The comparison takes into account the generation, the GA level and the feature bitmaps. In the case of a CPU generation/GA level mismatch a feature called "type" is reported to be missing. As a result, the output of virsh domcapabilities would change from something like ... <mode name='custom' supported='yes'> <model usable='unknown'>z10EC-base</model> <model usable='unknown'>z9EC-base</model> <model usable='unknown'>z196.2-base</model> <model usable='unknown'>z900-base</model> <model usable='unknown'>z990</model> ... to ... <mode name='custom' supported='yes'> <model usable='yes'>z10EC-base</model> <model usable='yes'>z9EC-base</model> <model usable='no'>z196.2-base</model> <model usable='yes'>z900-base</model> <model usable='yes'>z990</model> ... Signed-off-by: Viktor Mihajlovski <mihajlov@linux.vnet.ibm.com> Message-Id: <1499082529-16970-1-git-send-email-mihajlov@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-06-23target/s390x: Implement idte instructionDavid Hildenbrand5-0/+70
Let's keep it very simple for now and flush the complete tlb, we currently can't find the right entries in our tlb, we would have to store the used tables for each element. As we now fully implement the DAT-enhancement facility, we can allow to enable it for the qemu CPU model. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170622094151.28633-4-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Improve heuristic for ipteDavid Hildenbrand1-9/+16
If only the page index is set, most likely we don't have a valid virtual address. Let's do a full tlb flush for that case. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170622094151.28633-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Indicate and check for local tlb clearingDavid Hildenbrand3-3/+6
Let's allow to enable it for the qemu cpu model and correctly emulate it. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170622094151.28633-2-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Clean up TB flag bitsRichard Henderson2-23/+17
Most of the PSW bits that were being copied into TB->flags are not relevant to translation. Removing those that are unnecessary reduces the amount of translation required. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Finish implementing ETF2-ENHRichard Henderson2-3/+13
Missed the proper alignment in TRTO/TRTT, and ignoring the M3 field for all TRXX insns without ETF2-ENH. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Mark STFLE_49 facility as availableRichard Henderson1-0/+1
This facility bit includes execution-hint, load-and-trap, miscellaneous-instruction-extensions and processor-assist. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Implement processor-assist insnRichard Henderson2-0/+4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Implement execution-hint insnsRichard Henderson2-1/+13
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Mark STFLE_53 facility as availableRichard Henderson1-0/+1
This facility bit includes load-on-condition-2 and load-and-zero-rightmost-byte. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Implement load-and-zero-rightmost-byte insnsRichard Henderson2-0/+12
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Implement load-on-condition-2 insnsRichard Henderson3-3/+25
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Mark FPSEH facility as availableRichard Henderson1-0/+1
This facility bit includes DFP-rounding, FPR-GR-transfer, FPS-sign-handling, and IEEE-exception-simulation. We do support all of these. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: implement mvcos instructionDavid Hildenbrand6-15/+201
This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction. Allow to enable it for the qemu cpu model using qemu-system-s390x ... -cpu qemu,mvcos=on ... This allows to boot linux kernel that uses it for uacccess. We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode. We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used. user mode will always see a PRIVILEDGED exception. This patch is based on an original patch by Miroslav Benes (thanks!). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170614133819.18480-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: change PSW_SHIFT_KEYDavid Hildenbrand2-2/+2
Such shifts are usually used to easily extract the PSW KEY from the PSW mask, so let's avoid the confusing offset of 4. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170614133819.18480-2-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-23target/s390x: Map existing FAC_* names to S390_FEAT_* namesRichard Henderson1-30/+29
The FAC_ names were placeholders prior to the introduction of the current facility modeling. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-19target/s390x: Exit after changing PSW maskRichard Henderson1-4/+10
Exit to cpu loop so we reevaluate cpu_s390x_hw_interrupts. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-13s390x/cpumodel: wire up cpu type + id for TCGDavid Hildenbrand5-14/+16
Let's properly expose the CPU type (machine-type number) via "STORE CPU ID" and "STORE SUBSYSTEM INFORMATION". As TCG emulates basic mode, the CPU identification number has the format "Annnnn", whereby A is the CPU address, and n are parts of the CPU serial number (0 for us for now). A specification exception will be injected if the address is not aligned to a double word. Low address protection will not be checked as we're missing some more general support for that. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170609133426.11447-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-13target/s390x: rework PGM interrupt psw.addr handlingDavid Hildenbrand5-32/+49
We can tell from the program interrupt code, whether a program interrupt has to forward the address in the PGM new PSW (suppressing/terminated/completed) to point at the next instruction, or if it is nullifying and the PSW address does not have to be incremented. So let's not modify the PSW address outside of the injection path and handle this internally. We just have to handle instruction length auto detection if no valid instruction length can be provided. This should fix various program interrupt injection paths, where the PSW was not properly forwarded. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170609142156.18767-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-13target/s390x: correctly indicate PER nullificationDavid Hildenbrand1-0/+1
Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170609142156.18767-2-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-13Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170608' into ↵Peter Maydell4-3/+22
staging s390x: misc fixes bunch of fixes - reject MIDA accesses for CCWs - cpumodel fixes - cross-build fix for bios - migration improvements # gpg: Signature made Thu 08 Jun 2017 14:10:29 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20170608: s390x/cpumodel: improve defintion search without an IBC s390x/cpumodel: take care of the cpuid format bit for KVM pc-bios/s390-ccw: use STRIP variable in Makefile s390x/css: fence off MIDA s390x/css: catch section mismatch on load Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-06target/s390x: addressing exceptions are suppressingDavid Hildenbrand1-1/+1
We have to make the address in the old PSW point at the next instruction, as addressing exceptions are suppressing and not nullifying. I assume that there are a lot of other broken cases (as most instructions we care about are suppressing) - all trigger_pgm_exception() specifying and explicit number or ILEN_LATER look suspicious, however this is another story that might require bigger changes (and I have to understand when the address might already have been incremented first). This is needed to make an upcoming kvm-unit-test work. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170529121228.2789-1-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: mark ETF2 and ETF2-ENH facilities as availableAurelien Jarno1-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-30-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: check alignment in CDSG in the !CONFIG_ATOMIC128 caseAurelien Jarno1-0/+2
The CDSG instruction requires a 16-byte alignement, as expressed in the MO_ALIGN_16 passed to helper_atomic_cmpxchgo_be_mmu. In the non parallel case, use check_alignment to enforce this. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170604202034.16615-4-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement STORE PAIR TO QUADWORDAurelien Jarno4-0/+33
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170604202034.16615-3-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement LOAD PAIR FROM QUADWORDAurelien Jarno4-0/+37
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170604202034.16615-2-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement TRANSLATE ONE/TWO TO ONE/TWOAurelien Jarno4-0/+85
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-29-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement TEST DECIMALAurelien Jarno4-0/+36
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-28-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement UNPACK UNICODEAurelien Jarno4-10/+60
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-27-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement UNPACK ASCIIAurelien Jarno4-0/+71
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-26-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement PACK UNICODEAurelien Jarno4-9/+40
Use a common helper with PACK ASCII as the differences are limited to the stride of the source operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-25-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement PACK ASCIIAurelien Jarno4-0/+54
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-24-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement MOVE LONG UNICODEAurelien Jarno4-6/+65
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-23-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement COMPARE LOGICAL LONG UNICODEAurelien Jarno5-15/+90
For that we need to make program_interrupt available to qemu-user. Fortunately there is almost nothing to change as both kvm_enabled and CONFIG_KVM evaluate to false in that case. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-22-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: improve MOVE LONG and MOVE LONG EXTENDEDAurelien Jarno2-60/+70
As MVCL and MVCLE only differ by their operands, use a common do_mvcl helper. Optimize it calling fast_memmove and fast_memset. Correctly write back addresses. Check that r1 and r2/r3 registers are even. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-21-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: fix adj_len_to_pageAurelien Jarno1-1/+1
adj_len_to_page doesn't return the correct result when the address is already page aligned and the length is bigger than a page. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-20-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement COMPARE LOGICAL LONGAurelien Jarno4-23/+83
As CLCL and CLCLE mostly differ by their operands, use a common do_clcl helper. Another difference is that CLCL is not interruptible. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-19-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: fix COMPARE LOGICAL LONG EXTENDEDAurelien Jarno2-22/+52
There are multiple issues with the COMPARE LOGICAL LONG EXTENDED instruction: - The test between the two operands is inverted, leading to an inversion of the cc values 1 and 2. - The address and length of an operand continue to be decreased after reaching the end of this operand. These values are then wrong write back to the registers. - We should limit the amount of bytes to process, so that interrupts can be served correctly. At the same time rename dest into src1 and src into src3 to match the operand names and make the code less confusing. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-18-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: improve 24-bit and 31-bit lengths read/writeAurelien Jarno1-14/+33
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-17-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: improve 24-bit and 31-bit addresses writeAurelien Jarno1-7/+30
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-16-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: improve 24-bit and 31-bit addresses readAurelien Jarno1-40/+31
Improve fix_address to also handle the 24-bit mode. Rename fix_address to wrap_address to better explain what is changed. Replace the calls to get_address with x2 = 0 and b2 = 0 by call to wrap_address, leading to the removal of this function. Rename get_address_31fix into get_address. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-15-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement MOVE ZONESAurelien Jarno4-0/+24
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-14-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement MOVE WITH OFFSETAurelien Jarno4-0/+44
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-13-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement MOVE NUMERICSAurelien Jarno4-0/+24
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-12-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement MOVE INVERSEAurelien Jarno4-0/+23
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-11-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement COMPARE AND SIGNALAurelien Jarno4-0/+57
These functions differ from COMPARE by generating an exception for a QNaN input. Use the non quiet version of floatXX_compare. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-10-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement PACKAurelien Jarno4-0/+51
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-7-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement TEST ADDRESSING MODEAurelien Jarno2-0/+13
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-6-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-06target/s390x: implement TEST AND SETAurelien Jarno2-0/+13
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170531220129.27724-5-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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