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2019-03-11s390x/tcg: Implement VECTOR UNPACK *David Hildenbrand2-0/+46
2019-03-11s390x/tcg: Implement VECTOR STORE WITH LENGTHDavid Hildenbrand4-0/+40
2019-03-11s390x/tcg: Implement VECTOR STORE MULTIPLEDavid Hildenbrand2-0/+32
2019-03-11s390x/tcg: Implement VECTOR STORE ELEMENTDavid Hildenbrand2-0/+23
2019-03-11s390x/tcg: Implement VECTOR STOREDavid Hildenbrand2-0/+19
2019-03-11s390x/tcg: Provide probe_write_access helperDavid Hildenbrand3-0/+29
2019-03-11s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORDDavid Hildenbrand2-0/+35
2019-03-11s390x/tcg: Implement VECTOR SELECTDavid Hildenbrand2-0/+43
2019-03-11s390x/tcg: Implement VECTOR SCATTER ELEMENTDavid Hildenbrand2-0/+25
2019-03-11s390x/tcg: Implement VECTOR REPLICATE IMMEDIATEDavid Hildenbrand2-0/+16
2019-03-11s390x/tcg: Implement VECTOR REPLICATEDavid Hildenbrand2-0/+18
2019-03-11s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATEDavid Hildenbrand2-0/+18
2019-03-11s390x/tcg: Implement VECTOR PERMUTEDavid Hildenbrand4-0/+34
2019-03-11s390x/tcg: Implement VECTOR PACK *David Hildenbrand4-0/+215
2019-03-11s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)David Hildenbrand2-0/+46
2019-03-11s390x/tcg: Implement VECTOR LOAD WITH LENGTHDavid Hildenbrand3-0/+22
2019-03-11s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINTDavid Hildenbrand2-0/+9
2019-03-11s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GRDavid Hildenbrand2-0/+43
2019-03-11s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARYDavid Hildenbrand5-0/+75
2019-03-11s390x/tcg: Implement VECTOR LOAD MULTIPLEDavid Hildenbrand2-0/+42
2019-03-11s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERODavid Hildenbrand2-0/+48
2019-03-11s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENTDavid Hildenbrand2-0/+65
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATEDavid Hildenbrand2-0/+22
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENTDavid Hildenbrand2-0/+23
2019-03-11s390x/tcg: Implement VECTOR LOAD AND REPLICATEDavid Hildenbrand2-0/+21
2019-03-11s390x/tcg: Implement VECTOR LOADDavid Hildenbrand2-0/+27
2019-03-11s390x/tcg: Implement VECTOR GENERATE MASKDavid Hildenbrand2-0/+49
2019-03-11s390x/tcg: Implement VECTOR GENERATE BYTE MASKDavid Hildenbrand3-0/+42
2019-03-11s390x/tcg: Implement VECTOR GATHER ELEMENTDavid Hildenbrand3-0/+143
2019-03-11s390x/tcg: Utilities for vector instruction helpersDavid Hildenbrand1-0/+101
2019-03-11s390x/tcg: Check vector register instructions at central pointDavid Hildenbrand2-0/+19
2019-03-11s390x/tcg: Define vector instruction formatsDavid Hildenbrand2-1/+63
2019-03-11target/s390x: Remove non-architected entries from struct LowCoreThomas Huth1-39/+2
2019-03-04s390x: Add floating-point extension facility to "qemu" cpu modelDavid Hildenbrand1-0/+5
2019-03-04s390x/tcg: Handle all rounding modes overwritten by BFP instructionsDavid Hildenbrand1-2/+11
2019-03-04s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand4-15/+44
2019-03-04s390x/tcg: Implement XxC and checks for most FP instructionsDavid Hildenbrand2-126/+247
2019-03-04s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)David Hildenbrand1-57/+57
2019-03-04s390x/tcg: Refactor saving/restoring the bfp rounding modeDavid Hildenbrand2-43/+71
2019-03-04s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand4-35/+39
2019-03-04s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modesDavid Hildenbrand2-5/+19
2019-03-04s390x/tcg: Fix simulated-IEEE exceptionsDavid Hildenbrand1-0/+13
2019-03-04s390x/tcg: Refactor SET FPC AND SIGNAL handlingDavid Hildenbrand1-10/+12
2019-03-04s390x/tcg: Hide IEEE underflows in some scenariosDavid Hildenbrand1-0/+13
2019-03-04s390x/tcg: Fix parts of IEEE exception handlingDavid Hildenbrand1-6/+32
2019-03-04s390x/tcg: Factor out conversion of softfloat exceptionsDavid Hildenbrand2-12/+20
2019-03-04s390x/tcg: Fix rounding from float128 to uint64_t/uint32_tDavid Hildenbrand1-6/+2
2019-03-04s390x/tcg: Fix TEST DATA CLASS instructionsDavid Hildenbrand1-50/+35
2019-03-04s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARYDavid Hildenbrand5-0/+31
2019-03-04s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFPDavid Hildenbrand2-0/+8
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