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path: root/target/s390x/helper.h
AgeCommit message (Expand)AuthorFilesLines
2021-09-06s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKEDavid Hildenbrand1-3/+3
2021-07-07target/s390x: Fix CC set by CONVERT TO FIXED/LOGICALUlrich Weigand1-12/+12
2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand1-0/+6
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand1-0/+6
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand1-0/+4
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand1-0/+2
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand1-0/+1
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand1-0/+1
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand1-0/+4
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand1-0/+12
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand1-0/+4
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand1-0/+8
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand1-0/+1
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand1-1/+0
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand1-1/+0
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand1-2/+0
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand1-1/+0
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand1-6/+0
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand1-6/+0
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand1-4/+0
2021-03-15target/s390x: Store r1/r2 for page-translation exceptions during MVPGDavid Hildenbrand1-1/+1
2020-10-02s390x/tcg: Implement MONITOR CALLDavid Hildenbrand1-0/+1
2020-06-02target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson1-4/+0
2019-12-18target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson1-4/+0
2019-12-18target/s390x: Split out helper_per_store_realRichard Henderson1-0/+1
2019-09-23s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand1-1/+1
2019-06-07s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand1-0/+4
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand1-0/+12
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand1-0/+4
2019-06-07s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand1-0/+12
2019-06-07s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand1-0/+6
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand1-0/+6
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand1-0/+6
2019-06-07s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand1-0/+8
2019-05-17s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand1-0/+1
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand1-0/+1
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