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2020-07-02target/riscv: vector compress instructionLIU Zhiwei4-0/+64
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei4-0/+150
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei4-0/+155
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei2-0/+52
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei3-0/+67
2020-07-02target/riscv: integer extract instructionLIU Zhiwei2-0/+117
2020-07-02target/riscv: vector element index instructionLIU Zhiwei4-0/+56
2020-07-02target/riscv: vector iota instructionLIU Zhiwei4-0/+62
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei4-0/+98
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei4-0/+54
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei4-0/+55
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei4-0/+92
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei4-0/+54
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei4-0/+58
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei4-0/+24
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei4-0/+133
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei4-0/+103
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei4-0/+106
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei4-0/+56
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei4-0/+68
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei6-30/+107
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei4-0/+258
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei4-0/+118
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei4-0/+50
2020-07-02target/riscv: vector floating-point square-root instructionLIU Zhiwei4-0/+93
2020-07-02target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei4-0/+126
2020-07-02target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei4-0/+334
2020-07-02target/riscv: vector widening floating-point multiplyLIU Zhiwei4-0/+33
2020-07-02target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei4-0/+77
2020-07-02target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei4-0/+257
2020-07-02target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei4-0/+250
2020-07-02target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei4-0/+168
2020-07-02target/riscv: vector single-width scaling shift instructionsLIU Zhiwei4-0/+148
2020-07-02target/riscv: vector widening saturating scaled multiply-addLIU Zhiwei4-0/+243
2020-07-02target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei4-0/+122
2020-07-02target/riscv: vector single-width averaging add and subtractLIU Zhiwei4-0/+129
2020-07-02target/riscv: vector single-width saturating add and subtractLIU Zhiwei4-0/+444
2020-07-02target/riscv: vector integer merge and move instructionsLIU Zhiwei4-0/+225
2020-07-02target/riscv: vector widening integer multiply-add instructionsLIU Zhiwei4-0/+83
2020-07-02target/riscv: vector single-width integer multiply-add instructionsLIU Zhiwei4-0/+139
2020-07-02target/riscv: vector widening integer multiply instructionsLIU Zhiwei4-0/+84
2020-07-02target/riscv: vector integer divide instructionsLIU Zhiwei4-0/+125
2020-07-02target/riscv: vector single-width integer multiply instructionsLIU Zhiwei4-0/+214
2020-07-02target/riscv: vector integer min/max instructionsLIU Zhiwei4-0/+122
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei4-0/+246
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei4-0/+123
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei4-0/+165
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei4-0/+96
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei4-0/+294
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei4-0/+362
generated by cgit v1.1 at 2024-12-29 07:37:03 +0000