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2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis5-72/+39
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis14-150/+166
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis4-28/+56
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis3-14/+27
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2-20/+15
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2-7/+8
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2-7/+5
2021-05-11target/riscv: fix a typo with interrupt namesEmmanuel Blot1-1/+1
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang1-2/+4
2021-05-11target/riscv: Add ePMP support for the Ibex CPUAlistair Francis1-0/+1
2021-05-11target/riscv/pmp: Remove outdated commentAlistair Francis1-4/+0
2021-05-11target/riscv: Add a config option for ePMPHou Weiying2-0/+11
2021-05-11target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying1-8/+146
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying5-0/+76
2021-05-11target/riscv: Add the ePMP featureAlistair Francis1-0/+1
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying1-0/+3
2021-05-11target/riscv: Fix the PMP is locked check when using TORAlistair Francis1-10/+16
2021-05-11target/riscv: Fixup saturate subtract functionLIU Zhiwei1-4/+4
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink1-8/+12
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis4-36/+38
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2-261/+382
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis1-1/+5
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2-37/+46
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis3-24/+26
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K2-0/+2
2021-05-11target/riscv: Align the data type of reset vector addressDylan Jhong1-1/+1
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra7-72/+23
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer1-178/+1
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer3-13/+13
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer1-34/+34
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer1-1/+1
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer1-3/+4
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer1-11/+14
2021-03-22target/riscv: flush TLB pages if PMP permission has been changedJim Shu1-0/+4
2021-03-22target/riscv: add log of PMP permission checkingJim Shu1-0/+12
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu3-43/+125
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang1-1/+1
2021-03-11Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell1-1/+1
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé1-1/+1
2021-03-09Various spelling fixesMichael Tokarev1-1/+1
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang5-0/+210
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-7/+16
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2-2/+2
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