riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-04-29	target/riscv: rvk: add support for zbkb extension	Weiwei Li	5	-28/+174
2022-04-29	target/riscv: rvk: add cfg properties for zbk* and zk*	Weiwei Li	2	-0/+36
2022-04-29	target/riscv: Support configuarable marchid, mvendorid, mipid CSR values	Frank Chang	3	-4/+47
2022-04-22	target/riscv: cpu: Enable native debug feature	Bin Meng	1	-1/+1
2022-04-22	target/riscv: machine: Add debug state description	Bin Meng	1	-0/+32
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng	4	-0/+90
2022-04-22	target/riscv: cpu: Add a config option for native debug	Bin Meng	2	-1/+8
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng	3	-0/+82
2022-04-22	hw/intc: Make RISC-V ACLINT mtime MMIO register writable	Frank Chang	2	-6/+6
2022-04-22	target/riscv/pmp: fix NAPOT range computation overflow	Nicolas Pitre	1	-11/+3
2022-04-22	target/riscv: Use cpu_loop_exit_restore directly from mmu faults	Richard Henderson	1	-3/+3
2022-04-22	target/riscv: fix start byte for vmv<nf>r.v when vstart != 0	Weiwei Li	1	-3/+5
2022-04-22	target/riscv: Add isa extenstion strings to the device tree	Atish Patra	1	-0/+60
2022-04-22	target/riscv: misa to ISA string conversion fix	Tsukasa OI	1	-5/+5
2022-04-22	target/riscv: optimize helper for vmv<nr>r.v	Weiwei Li	3	-33/+18
2022-04-22	target/riscv: optimize condition assign for scale < 0	Weiwei Li	1	-5/+3
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng	4	-0/+453
2022-04-22	target/riscv: Allow software access to MIP SEIP	Alistair Francis	3	-3/+23
2022-04-22	target/riscv: cpu: Fixup indentation	Alistair Francis	1	-10/+10
2022-04-22	target/riscv: Enable privileged spec version 1.12	Atish Patra	2	-3/+10
2022-04-22	target/riscv: Add envcfg CSRs support	Atish Patra	4	-0/+174
2022-04-22	target/riscv: Add support for mconfigptr	Atish Patra	2	-0/+3
2022-04-22	target/riscv: Introduce privilege version field in the CSR ops.	Atish Patra	2	-35/+70
2022-04-22	target/riscv: Add the privileged spec version 1.12.0	Atish Patra	1	-0/+1
2022-04-22	target/riscv: Define simpler privileged spec version numbering	Atish Patra	1	-2/+5
2022-04-21	compiler.h: replace QEMU_NORETURN with G_NORETURN	Marc-André Lureau	2	-7/+7
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson	1	-4/+6
2022-04-06	Remove qemu-common.h include from most units	Marc-André Lureau	1	-1/+0
2022-04-06	Move CPU softfloat unions to cpu-float.h	Marc-André Lureau	1	-1/+1
2022-04-06	Replace config-time define HOST_WORDS_BIGENDIAN	Marc-André Lureau	2	-3/+3
2022-04-01	target/riscv: rvv: Add missing early exit condition for whole register load/s...	Yueh-Ting (eop) Chen	1	-0/+5
2022-04-01	target/riscv: Avoid leaking "no translation" TLB entries	Palmer Dabbelt	1	-6/+8
2022-03-06	target: Use ArchCPU as interface to target CPU	Philippe Mathieu-Daudé	1	-1/+1
2022-03-06	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	Philippe Mathieu-Daudé	1	-3/+1
2022-03-06	target: Use CPUArchState as interface to target-specific CPU state	Philippe Mathieu-Daudé	1	-3/+2
2022-03-06	target: Include missing 'cpu.h'	Philippe Mathieu-Daudé	1	-0/+2
2022-03-06	misc: Add missing "sysemu/cpu-timers.h" include	Philippe Mathieu-Daudé	1	-0/+1
2022-03-03	target/riscv: expose zfinx, zdinx, zhinx{min} properties	Weiwei Li	1	-0/+5
2022-03-03	target/riscv: add support for zhinx/zhinxmin	Weiwei Li	4	-143/+296
2022-03-03	target/riscv: add support for zdinx	Weiwei Li	2	-78/+259
2022-03-03	target/riscv: add support for zfinx	Weiwei Li	5	-145/+369
2022-03-03	target/riscv: hardwire mstatus.FS to zero when enable zfinx	Weiwei Li	3	-6/+29
2022-03-03	target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}	Weiwei Li	2	-0/+16
2022-03-03	target/riscv: fix inverted checks for ext_zb[abcs]	Philipp Tomsich	1	-4/+4
2022-02-21	target: Add missing "qemu/timer.h" include	Philippe Mathieu-Daudé	1	-0/+1
2022-02-16	target/riscv: add support for svpbmt extension	Weiwei Li	3	-1/+6
2022-02-16	target/riscv: add support for svinval extension	Weiwei Li	5	-0/+85
2022-02-16	target/riscv: add support for svnapot extension	Weiwei Li	3	-3/+18
2022-02-16	target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE	Weiwei Li	1	-0/+3
2022-02-16	target/riscv: Ignore reserved bits in PTE for RV64	Guo Ren	3	-1/+30