aboutsummaryrefslogtreecommitdiff
path: root/target/riscv
AgeCommit message (Expand)AuthorFilesLines
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood6-0/+397
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk2-42/+46
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood1-29/+23
2023-09-11target/riscv: Move vector translation checksNazar Kazakov1-16/+12
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter8-1/+146
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov1-30/+1
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk1-30/+32
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk4-200/+265
2023-09-11target/riscv: Use existing lookup tables for MixColumnsArd Biesheuvel1-30/+4
2023-09-11target/riscv: Fix page_check_range use in fault-only-firstLIU Zhiwei1-1/+1
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza1-0/+5
2023-09-08riscv: spelling fixesMichael Tokarev8-17/+17
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé4-4/+0
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2-0/+2
2023-08-31target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé2-1/+1
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson1-1/+1
2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki1-0/+5
2023-08-11target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()Daniel Henrique Barboza1-1/+8
2023-07-19target/riscv: Fix LMUL check to use VLENRob Bradford1-2/+2
2023-07-19target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcfDaniel Henrique Barboza1-1/+2
2023-07-15accel/tcg: Return bool from page_check_rangeRichard Henderson1-1/+1
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner7-0/+730
2023-07-10target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVMDaniel Henrique Barboza1-0/+70
2023-07-10target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helperDaniel Henrique Barboza1-4/+7
2023-07-10target/riscv: update multi-letter extension KVM propertiesDaniel Henrique Barboza1-0/+27
2023-07-10target/riscv/cpu.c: create KVM mock propertiesDaniel Henrique Barboza1-0/+36
2023-07-10target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()Daniel Henrique Barboza1-2/+1
2023-07-10target/riscv/cpu.c: add satp_mode properties earlierDaniel Henrique Barboza1-4/+2
2023-07-10target/riscv/kvm.c: add multi-letter extension KVM propertiesDaniel Henrique Barboza2-0/+127
2023-07-10target/riscv/kvm.c: update KVM MISA bitsDaniel Henrique Barboza1-0/+40
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza2-0/+83
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza2-29/+88
2023-07-10target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPUDaniel Henrique Barboza1-11/+23
2023-07-10target/riscv: handle mvendorid/marchid/mimpid for KVM CPUsDaniel Henrique Barboza1-0/+31
2023-07-10target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()Daniel Henrique Barboza1-0/+16
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza3-0/+92
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza1-7/+53
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza1-2/+32
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza1-1/+37
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza1-10/+25
2023-07-10target/riscv KVM_RISCV_SET_TIMER macro is not configured correctlyyang.zhang1-1/+1
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien1-1/+0
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li1-0/+7
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li4-0/+76
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li4-0/+77
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li6-6/+80
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li2-0/+23
generated by cgit v1.1 at 2025-02-12 18:06:14 +0000