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2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-8/+8
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng1-2/+2
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis1-5/+9
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis3-26/+24
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis4-41/+63
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis1-1/+1
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng1-4/+4
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng1-21/+10
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng1-14/+6
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng1-13/+5
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang1-2/+15
2020-06-08Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell1-2/+4
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé1-2/+4
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis2-0/+11
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis1-5/+0
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis1-2/+3
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis1-1/+2
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis7-200/+63
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis2-35/+0
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton2-0/+11
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel1-6/+1
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis1-3/+5
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis1-1/+2
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-4/+5
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2-4/+5
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée2-11/+11
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal1-1/+8
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis1-1/+1
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt1-2/+2
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel3-4/+92
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2-0/+6
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis4-4/+15
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis6-0/+62
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis2-19/+175
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Remove the hret instructionAlistair Francis2-6/+0
2020-02-27target/riscv: Add hfence instructionsAlistair Francis2-9/+54
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis1-10/+52
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis1-2/+3
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
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