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2023-03-01target/riscv: Allow debugger to access sstc CSRsBin Meng1-5/+14
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng1-2/+20
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng1-0/+4
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng1-0/+4
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng1-75/+0
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng1-0/+9
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng1-15/+9
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng1-24/+12
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng1-2/+2
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng1-1/+1
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng1-30/+32
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng1-3/+6
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng1-2/+2
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng1-5/+1
2023-03-01target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...Bin Meng1-1/+10
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng1-0/+3
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza2-15/+2
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza6-16/+5
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza7-11/+5
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza4-11/+6
2023-03-01target/riscv/cpu.c: error out if EPMP is enabled without PMPDaniel Henrique Barboza1-2/+7
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza5-10/+4
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza3-2/+8
2023-03-01target/riscv: do not mask unsupported QEMU extensions in write_misa()Daniel Henrique Barboza1-3/+0
2023-03-01target/riscv: introduce riscv_cpu_cfg()Daniel Henrique Barboza1-0/+5
2023-02-27target/riscv/cpu: Move Floating-Point fields closerPhilippe Mathieu-Daudé1-3/+3
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé1-5/+5
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei1-2/+2
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza1-1/+1
2023-02-23target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan1-3/+6
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang2-15/+8
2023-02-08riscv: Clean up includesMarkus Armbruster1-1/+0
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev1-2/+3
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev1-0/+1
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner5-3/+55
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner3-0/+38
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner5-1/+123
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner5-1/+464
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner5-1/+109
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner5-1/+96
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner5-1/+43
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner5-1/+23
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner5-2/+149
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner5-1/+66
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner7-1/+105
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner6-0/+131
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich2-1/+6
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