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AgeCommit message (Expand)AuthorFilesLines
2023-10-07meson: Rename target_softmmu_arch -> target_system_archPhilippe Mathieu-Daudé1-1/+1
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-1/+1
2023-10-04accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson1-5/+1
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-3/+3
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson16-236/+236
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson1-1/+1
2023-10-03target/*: Add instance_align to all cpu base classesRichard Henderson1-1/+1
2023-09-29target/riscv: vector_helper: Fixup local variables shadowingAlistair Francis1-3/+4
2023-09-29target/riscv: cpu: Fixup local variables shadowingAlistair Francis1-2/+2
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin1-9/+15
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu1-2/+5
2023-09-11target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changesLeon Schuermann1-0/+4
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki3-5/+21
2023-09-11target/riscv: Use accelerated helper for AES64KS1IArd Biesheuvel1-12/+5
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza2-0/+6
2023-09-11riscv: zicond: make non-experimentalVineet Gupta1-1/+1
2023-09-11target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0Daniel Henrique Barboza1-3/+20
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li4-15/+15
2023-09-11target/riscv: Create an KVM AIA irqchipYong-Xuan Wang2-0/+190
2023-09-11target/riscv: check the in-kernel irqchip supportYong-Xuan Wang1-1/+9
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei1-2/+2
2023-09-11target/riscv: Add Zihintntl extension ISA string to DTSJason Chien2-0/+3
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford1-2/+9
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou6-1/+184
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov6-2/+114
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter6-2/+177
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk6-3/+390
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov6-1/+381
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood6-0/+397
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk2-42/+46
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood1-29/+23
2023-09-11target/riscv: Move vector translation checksNazar Kazakov1-16/+12
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter8-1/+146
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov1-30/+1
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk1-30/+32
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk4-200/+265
2023-09-11target/riscv: Use existing lookup tables for MixColumnsArd Biesheuvel1-30/+4
2023-09-11target/riscv: Fix page_check_range use in fault-only-firstLIU Zhiwei1-1/+1
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza1-0/+5
2023-09-08riscv: spelling fixesMichael Tokarev8-17/+17
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé4-4/+0
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2-0/+2
2023-08-31target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé2-1/+1
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson1-1/+1
2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki1-0/+5
2023-08-11target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()Daniel Henrique Barboza1-1/+8
2023-07-19target/riscv: Fix LMUL check to use VLENRob Bradford1-2/+2
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