Age | Commit message (Expand) | Author | Files | Lines |
2020-03-05 | RISC-V: Add a missing "," in riscv_excp_names | Palmer Dabbelt | 1 | -2/+2 |
2020-02-27 | target/riscv: Emulate TIME CSRs for privileged mode | Anup Patel | 3 | -4/+92 |
2020-02-27 | target/riscv: Allow enabling the Hypervisor extension | Alistair Francis | 2 | -0/+6 |
2020-02-27 | target/riscv: Add the MSTATUS_MPV_ISSET helper macro | Alistair Francis | 4 | -4/+15 |
2020-02-27 | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis | 6 | -0/+62 |
2020-02-27 | target/riscv: Set htval and mtval2 on execptions | Alistair Francis | 1 | -0/+10 |
2020-02-27 | target/riscv: Raise the new execptions when 2nd stage translation fails | Alistair Francis | 1 | -6/+18 |
2020-02-27 | target/riscv: Implement second stage MMU | Alistair Francis | 2 | -19/+175 |
2020-02-27 | target/riscv: Allow specifying MMU stage | Alistair Francis | 1 | -9/+28 |
2020-02-27 | target/riscv: Respect MPRV and SPRV for floating point ops | Alistair Francis | 1 | -1/+15 |
2020-02-27 | target/riscv: Mark both sstatus and msstatus_hs as dirty | Alistair Francis | 1 | -0/+13 |
2020-02-27 | target/riscv: Disable guest FP support based on virtual status | Alistair Francis | 1 | -0/+3 |
2020-02-27 | target/riscv: Only set TB flags with FP status if enabled | Alistair Francis | 1 | -1/+4 |
2020-02-27 | target/riscv: Remove the hret instruction | Alistair Francis | 2 | -6/+0 |
2020-02-27 | target/riscv: Add hfence instructions | Alistair Francis | 2 | -9/+54 |
2020-02-27 | target/riscv: Add Hypervisor trap return support | Alistair Francis | 1 | -10/+52 |
2020-02-27 | target/riscv: Add hypvervisor trap support | Alistair Francis | 1 | -10/+59 |
2020-02-27 | target/riscv: Generate illegal instruction on WFI when V=1 | Alistair Francis | 1 | -2/+3 |
2020-02-27 | target/ricsv: Flush the TLB on virtulisation mode changes | Alistair Francis | 1 | -0/+5 |
2020-02-27 | target/riscv: Add support for virtual interrupt setting | Alistair Francis | 1 | -5/+28 |
2020-02-27 | target/riscv: Extend the SIP CSR to support virtulisation | Alistair Francis | 1 | -1/+12 |
2020-02-27 | target/riscv: Extend the MIE CSR to support virtulisation | Alistair Francis | 1 | -4/+20 |
2020-02-27 | target/riscv: Set VS bits in mideleg for Hyp extension | Alistair Francis | 1 | -0/+3 |
2020-02-27 | target/riscv: Add virtual register swapping function | Alistair Francis | 3 | -0/+79 |
2020-02-27 | target/riscv: Add Hypervisor machine CSRs accesses | Alistair Francis | 1 | -0/+27 |
2020-02-27 | target/riscv: Add Hypervisor virtual CSRs accesses | Alistair Francis | 1 | -0/+116 |
2020-02-27 | target/riscv: Add Hypervisor CSR access functions | Alistair Francis | 1 | -2/+134 |
2020-02-27 | target/riscv: Dump Hypervisor registers if enabled | Alistair Francis | 1 | -0/+33 |
2020-02-27 | target/riscv: Print priv and virt in disas log | Alistair Francis | 1 | -0/+8 |
2020-02-27 | target/riscv: Fix CSR perm checking for HS mode | Alistair Francis | 1 | -4/+14 |
2020-02-27 | target/riscv: Add the force HS exception mode | Alistair Francis | 3 | -0/+26 |
2020-02-27 | target/riscv: Add the virtulisation mode | Alistair Francis | 3 | -0/+25 |
2020-02-27 | target/riscv: Rename the H irqs to VS irqs | Alistair Francis | 2 | -9/+9 |
2020-02-27 | target/riscv: Add support for the new execption numbers | Alistair Francis | 4 | -20/+37 |
2020-02-27 | target/riscv: Add the Hypervisor CSRs to CPUState | Alistair Francis | 3 | -18/+48 |
2020-02-27 | target/riscv: Add the Hypervisor extension | Alistair Francis | 1 | -0/+1 |
2020-02-27 | target/riscv: Convert MIP CSR to target_ulong | Alistair Francis | 2 | -2/+2 |
2020-02-25 | target/riscv: progressively load the instruction during decode | Alex Bennée | 2 | -23/+25 |
2020-02-10 | riscv: Separate FPU register size from core register size in gdbstub [v2] | Keith Packard | 1 | -9/+11 |
2020-01-27 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell | 1 | -3/+2 |
2020-01-24 | qdev: set properties with device_class_set_props() | Marc-André Lureau | 1 | -1/+1 |
2020-01-24 | cpu: Use cpu_class_set_parent_reset() | Greg Kurz | 1 | -2/+1 |
2020-01-24 | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i... | Peter Maydell | 6 | -11/+5 |
2020-01-16 | target/riscv: update mstatus.SD when FS is set dirty | ShihPo Hung | 2 | -3/+2 |
2020-01-16 | target/riscv: fsd/fsw doesn't dirty FP state | ShihPo Hung | 2 | -2/+0 |
2020-01-16 | target/riscv: Fix tb->flags FS status | ShihPo Hung | 1 | -4/+1 |
2020-01-16 | riscv: Set xPIE to 1 after xRET | Yiting Wang | 1 | -2/+2 |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 2 | -2/+2 |
2019-11-14 | target/riscv: Remove atomic accesses to MIP CSR | Alistair Francis | 4 | -43/+21 |
2019-11-14 | remove unnecessary ifdef TARGET_RISCV64 | hiroyuki.obinata | 1 | -3/+1 |