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AgeCommit message (Expand)AuthorFilesLines
2023-07-10target/riscv: Add RVV registers to logIvan Klokov1-1/+56
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li2-9/+25
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li3-8/+55
2023-07-10target/riscv/cpu.c: fix veyron-v1 CPU propertiesDaniel Henrique Barboza1-0/+3
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li1-4/+0
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li1-6/+4
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li2-2/+4
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner1-0/+11
2023-07-10target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner2-25/+28
2023-07-10target/riscv: Use xl instead of mxl for disassembleLIU Zhiwei1-1/+2
2023-07-09target/riscv: Use aesdec_ISB_ISR_IMC_AKRichard Henderson1-91/+10
2023-07-09target/riscv: Use aesenc_SB_SR_MC_AKRichard Henderson1-1/+6
2023-07-09target/riscv: Use aesdec_IMCRichard Henderson1-10/+5
2023-07-09target/riscv: Use aesdec_ISB_ISR_AKRichard Henderson1-1/+6
2023-07-09target/riscv: Use aesenc_SB_SR_AKRichard Henderson1-1/+9
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé3-3/+9
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson2-4/+4
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-3/+3
2023-06-13target/riscv: Smepmp: Return error when access permission not allowed in PMPHimanshu Chauhan1-8/+2
2023-06-13target/riscv/vector_helper.c: Remove the check for extra tail elementsXiao Wang1-16/+6
2023-06-13target/riscv/vector_helper.c: clean up reference of MTYPEXiao Wang1-5/+1
2023-06-13target/riscv: Fix initialized value for cur_pmmaskWeiwei Li1-2/+2
2023-06-13target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li1-6/+1
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li4-20/+74
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li3-12/+9
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li6-13/+13
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li2-5/+7
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li1-1/+3
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li3-20/+28
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li1-0/+1
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li2-113/+137
2023-06-13target/riscv: smstateen knobsMayuresh Chitale1-1/+2
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale2-3/+10
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale1-0/+15
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li1-1/+8
2023-06-13target/riscv: Fix pointer mask transformation for vector addressWeiwei Li1-1/+1
2023-06-13target/riscv: Deny access if access is partially inside the PMP entryWeiwei Li1-2/+2
2023-06-13target/riscv: Separate pmp_update_rule() in pmpcfg_csr_writeWeiwei Li1-14/+2
2023-06-13target/riscv: Flush TLB only when pmpcfg/pmpaddr really changesWeiwei Li1-10/+18
2023-06-13target/riscv: Flush TLB when pmpaddr is updatedWeiwei Li1-0/+1
2023-06-13target/riscv: Update the next rule addr in pmpaddr_csr_write()Weiwei Li1-3/+7
2023-06-13target/riscv: Flush TLB when MMWP or MML bits are changedWeiwei Li1-0/+3
2023-06-13target/riscv: Remove unused paramters in pmp_hart_has_privs_default()Weiwei Li1-6/+3
2023-06-13target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabledWeiwei Li1-24/+26
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li3-27/+21
2023-06-13target/riscv: Make the short cut really work in pmp_hart_has_privsWeiwei Li1-0/+1
2023-06-13target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmpWeiwei Li1-10/+6
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li3-22/+57
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza3-29/+27
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza1-12/+47
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