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AgeCommit message (Expand)AuthorFilesLines
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson3-20/+25
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson1-44/+45
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson3-52/+97
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2-17/+32
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson1-1/+6
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2-3/+39
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson4-43/+62
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson1-12/+14
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson1-1/+2
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson5-1/+47
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson6-32/+43
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson6-67/+98
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson1-3/+5
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2-45/+48
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis1-7/+10
2021-10-22target/riscv: Remove some unused macrosAlistair Francis1-8/+0
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2-8/+8
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich1-5/+8
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht1-5/+5
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang1-1/+2
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson4-34/+7
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson1-5/+1
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2-13/+21
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich3-33/+0
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2-77/+21
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich4-79/+15
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich1-0/+6
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich4-55/+18
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2-41/+50
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich4-1/+65
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2-18/+24
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2-78/+0
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2-63/+0
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2-13/+23
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2-0/+8
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich1-3/+5
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich1-1/+1
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich1-2/+4
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-1/+1
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2-16/+16
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis1-0/+30
2021-09-21target/riscv: Fix satp writeLIU Zhiwei1-1/+1
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis2-2/+3
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé3-7/+2
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-2/+3
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2-61/+26
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson2-210/+57
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